Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	276789	1			T1	1		T2	15		T7	1
all_pins[1]	276789	1			T1	1		T2	15		T7	1
all_pins[2]	276789	1			T1	1		T2	15		T7	1
all_pins[3]	276789	1			T1	1		T2	15		T7	1
all_pins[4]	276789	1			T1	1		T2	15		T7	1
all_pins[5]	276789	1			T1	1		T2	15		T7	1
all_pins[6]	276789	1			T1	1		T2	15		T7	1
all_pins[7]	276789	1			T1	1		T2	15		T7	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2213397	1			T1	8		T2	100		T7	8
values[0x1]	915	1			T2	20		T34	44		T41	15
transitions[0x0=>0x1]	707	1			T2	15		T34	33		T41	12
transitions[0x1=>0x0]	719	1			T2	16		T34	34		T41	12

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	276680	1			T1	1		T2	15		T7	1
all_pins[0]	values[0x1]	109	1			T34	5		T40	9		T360	2
all_pins[0]	transitions[0x0=>0x1]	79	1			T34	4		T40	8		T360	1
all_pins[0]	transitions[0x1=>0x0]	88	1			T2	5		T41	4		T40	2
all_pins[1]	values[0x0]	276671	1			T1	1		T2	10		T7	1
all_pins[1]	values[0x1]	118	1			T2	5		T34	1		T41	4
all_pins[1]	transitions[0x0=>0x1]	92	1			T2	4		T34	1		T41	2
all_pins[1]	transitions[0x1=>0x0]	82	1			T2	1		T34	7		T40	3
all_pins[2]	values[0x0]	276681	1			T1	1		T2	13		T7	1
all_pins[2]	values[0x1]	108	1			T2	2		T34	7		T41	2
all_pins[2]	transitions[0x0=>0x1]	85	1			T2	2		T34	6		T41	2
all_pins[2]	transitions[0x1=>0x0]	88	1			T2	1		T34	3		T41	1
all_pins[3]	values[0x0]	276678	1			T1	1		T2	14		T7	1
all_pins[3]	values[0x1]	111	1			T2	1		T34	4		T41	1
all_pins[3]	transitions[0x0=>0x1]	82	1			T34	2		T41	1		T40	5
all_pins[3]	transitions[0x1=>0x0]	108	1			T2	2		T34	6		T41	1
all_pins[4]	values[0x0]	276652	1			T1	1		T2	12		T7	1
all_pins[4]	values[0x1]	137	1			T2	3		T34	8		T41	1
all_pins[4]	transitions[0x0=>0x1]	111	1			T2	3		T34	8		T41	1
all_pins[4]	transitions[0x1=>0x0]	85	1			T2	1		T34	3		T41	3
all_pins[5]	values[0x0]	276678	1			T1	1		T2	14		T7	1
all_pins[5]	values[0x1]	111	1			T2	1		T34	3		T41	3
all_pins[5]	transitions[0x0=>0x1]	91	1			T2	1		T34	2		T41	3
all_pins[5]	transitions[0x1=>0x0]	89	1			T2	3		T34	9		T41	2
all_pins[6]	values[0x0]	276680	1			T1	1		T2	12		T7	1
all_pins[6]	values[0x1]	109	1			T2	3		T34	10		T41	2
all_pins[6]	transitions[0x0=>0x1]	84	1			T2	1		T34	5		T41	1
all_pins[6]	transitions[0x1=>0x0]	87	1			T2	3		T34	1		T41	1
all_pins[7]	values[0x0]	276677	1			T1	1		T2	10		T7	1
all_pins[7]	values[0x1]	112	1			T2	5		T34	6		T41	2
all_pins[7]	transitions[0x0=>0x1]	83	1			T2	4		T34	5		T41	2
all_pins[7]	transitions[0x1=>0x0]	92	1			T34	5		T40	7		T360	2