Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
65.07	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	51	77	60.16

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	51	77	60.16	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	350	1			T7	2		T193	2		T101	12
values[1]	530	1			T5	26		T6	30		T43	26
values[2]	356	1			T44	34		T78	16		T79	22
values[3]	416	1			T46	12		T194	6		T130	18
values[4]	386	1			T11	10		T96	2		T28	10
values[5]	292	1			T49	4		T26	18		T45	18
values[6]	458	1			T9	10		T12	6		T73	10
values[7]	464	1			T120	6		T195	24		T47	10

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	412	1			T196	14		T197	14		T198	18
values[1]	554	1			T6	30		T49	4		T43	26
values[2]	302	1			T7	2		T9	10		T11	10
values[3]	462	1			T46	12		T127	12		T72	10
values[4]	430	1			T5	26		T199	12		T200	10
values[5]	498	1			T12	6		T73	10		T47	10
values[6]	228	1			T195	24		T79	22		T96	2
values[7]	366	1			T78	16		T130	18		T97	16

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3184

1

T7

2

T5

26

T6

24

auto[1]

68

1

T6

6

T74

2

T75

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	51	77	60.16	51

Automatically Generated Cross Bins for cr_all

Element holes

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	8

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[values[6]]	0	1	1
[auto[1]]	[values[1]]	[values[0]]	0	1	1
[auto[1]]	[values[1]]	[values[2] , values[3]]	--	--	2
[auto[1]]	[values[1]]	[values[6]]	0	1	1
[auto[1]]	[values[2]]	[values[0] , values[1] , values[2] , values[3]]	--	--	4
[auto[1]]	[values[2]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[3]]	[values[0]]	0	1	1
[auto[1]]	[values[3]]	[values[2] , values[3] , values[4] , values[5] , values[6] , values[7]]	--	--	6
[auto[1]]	[values[4]]	[values[0] , values[1] , values[2] , values[3]]	--	--	4
[auto[1]]	[values[4]]	[values[5] , values[6] , values[7]]	--	--	3
[auto[1]]	[values[5]]	[values[0] , values[1] , values[2]]	--	--	3
[auto[1]]	[values[5]]	[values[4] , values[5]]	--	--	2
[auto[1]]	[values[5]]	[values[7]]	0	1	1
[auto[1]]	[values[6]]	[values[0]]	0	1	1
[auto[1]]	[values[6]]	[values[2] , values[3] , values[4] , values[5] , values[6] , values[7]]	--	--	6
[auto[1]]	[values[7]]	[values[1] , values[2] , values[3]]	--	--	3
[auto[1]]	[values[7]]	[values[5] , values[6]]	--	--	2

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	114	1			T201	6		T202	30		T203	36
auto[0]	values[0]	values[1]	72	1			T193	2		T101	12		T204	22
auto[0]	values[0]	values[2]	8	1			T7	2		T205	6		-	-
auto[0]	values[0]	values[3]	48	1			T206	6		T207	20		T208	22
auto[0]	values[0]	values[4]	36	1			T102	6		T190	20		T209	10
auto[0]	values[0]	values[5]	46	1			T181	8		T210	8		T8	30
auto[0]	values[0]	values[7]	26	1			T191	20		T211	6		-	-
auto[0]	values[1]	values[0]	56	1			T197	14		T198	18		T212	10
auto[0]	values[1]	values[1]	162	1			T6	24		T43	26		T213	38
auto[0]	values[1]	values[2]	40	1			T63	8		T214	20		T215	12
auto[0]	values[1]	values[3]	40	1			T127	12		T216	18		T217	8
auto[0]	values[1]	values[4]	62	1			T5	26		T183	2		T218	34
auto[0]	values[1]	values[5]	78	1			T219	14		T220	10		T221	16
auto[0]	values[1]	values[6]	12	1			T222	12		-	-		-	-
auto[0]	values[1]	values[7]	54	1			T189	16		T83	12		T223	12
auto[0]	values[2]	values[0]	26	1			T224	26		-	-		-	-
auto[0]	values[2]	values[1]	46	1			T44	34		T225	12		-	-
auto[0]	values[2]	values[2]	36	1			T23	12		T226	6		T227	6
auto[0]	values[2]	values[3]	34	1			T228	6		T229	28		-	-
auto[0]	values[2]	values[4]	64	1			T230	14		T231	2		T232	32
auto[0]	values[2]	values[5]	56	1			T48	12		T80	18		T233	2
auto[0]	values[2]	values[6]	40	1			T79	22		T234	12		T235	6
auto[0]	values[2]	values[7]	32	1			T78	16		T25	14		T188	2
auto[0]	values[3]	values[0]	74	1			T196	14		T236	14		T237	16
auto[0]	values[3]	values[1]	72	1			T194	6		T238	20		T93	20
auto[0]	values[3]	values[2]	70	1			T239	10		T240	6		T241	2
auto[0]	values[3]	values[3]	40	1			T46	12		T242	28		-	-
auto[0]	values[3]	values[4]	30	1			T29	26		T243	4		-	-
auto[0]	values[3]	values[5]	36	1			T244	22		T245	14		-	-
auto[0]	values[3]	values[6]	28	1			T246	2		T247	6		T248	20
auto[0]	values[3]	values[7]	64	1			T130	18		T97	16		T86	4
auto[0]	values[4]	values[0]	28	1			T249	2		T250	26		-	-
auto[0]	values[4]	values[1]	26	1			T61	10		T251	16		-	-
auto[0]	values[4]	values[2]	16	1			T11	10		T252	6		-	-
auto[0]	values[4]	values[3]	72	1			T253	28		T254	2		T255	14
auto[0]	values[4]	values[4]	36	1			T74	28		T256	8		-	-
auto[0]	values[4]	values[5]	52	1			T257	2		T92	4		T103	14
auto[0]	values[4]	values[6]	74	1			T96	2		T258	32		T259	2
auto[0]	values[4]	values[7]	80	1			T28	10		T260	24		T261	10
auto[0]	values[5]	values[0]	16	1			T262	4		T263	12		-	-
auto[0]	values[5]	values[1]	64	1			T49	4		T26	18		T45	18
auto[0]	values[5]	values[2]	30	1			T264	30		-	-		-	-
auto[0]	values[5]	values[3]	82	1			T265	8		T266	22		T267	20
auto[0]	values[5]	values[4]	14	1			T268	14		-	-		-	-
auto[0]	values[5]	values[5]	20	1			T76	14		T269	6		-	-
auto[0]	values[5]	values[6]	10	1			T270	8		T271	2		-	-
auto[0]	values[5]	values[7]	52	1			T272	8		T273	38		T274	6
auto[0]	values[6]	values[0]	58	1			T275	2		T276	30		T277	26
auto[0]	values[6]	values[1]	76	1			T27	30		T84	30		T278	16
auto[0]	values[6]	values[2]	70	1			T9	10		T279	14		T184	14
auto[0]	values[6]	values[3]	52	1			T72	10		T280	18		T281	24
auto[0]	values[6]	values[4]	82	1			T200	10		T282	10		T283	22
auto[0]	values[6]	values[5]	76	1			T12	6		T73	10		T116	8
auto[0]	values[6]	values[6]	24	1			T284	18		T285	6		-	-
auto[0]	values[6]	values[7]	18	1			T94	2		T286	16		-	-
auto[0]	values[7]	values[0]	34	1			T187	18		T287	16		-	-
auto[0]	values[7]	values[1]	16	1			T24	4		T288	10		T289	2
auto[0]	values[7]	values[2]	32	1			T120	6		T290	14		T118	10
auto[0]	values[7]	values[3]	92	1			T291	24		T292	4		T293	22
auto[0]	values[7]	values[4]	92	1			T199	12		T294	10		T75	16
auto[0]	values[7]	values[5]	116	1			T47	10		T295	14		T296	14
auto[0]	values[7]	values[6]	38	1			T195	24		T297	4		T298	10
auto[0]	values[7]	values[7]	34	1			T299	4		T300	2		T55	22
auto[1]	values[1]	values[1]	16	1			T6	6		T301	10		-	-
auto[1]	values[1]	values[4]	4	1			T218	4		-	-		-	-
auto[1]	values[1]	values[5]	2	1			T85	2		-	-		-	-
auto[1]	values[1]	values[7]	4	1			T83	4		-	-		-	-
auto[1]	values[2]	values[4]	6	1			T302	6		-	-		-	-
auto[1]	values[2]	values[5]	16	1			T80	10		T81	6		-	-
auto[1]	values[3]	values[1]	2	1			T303	2		-	-		-	-
auto[1]	values[4]	values[4]	2	1			T74	2		-	-		-	-
auto[1]	values[5]	values[3]	2	1			T82	2		-	-		-	-
auto[1]	values[5]	values[6]	2	1			T271	2		-	-		-	-
auto[1]	values[6]	values[1]	2	1			T84	2		-	-		-	-
auto[1]	values[7]	values[0]	6	1			T287	6		-	-		-	-
auto[1]	values[7]	values[4]	2	1			T75	2		-	-		-	-
auto[1]	values[7]	values[7]	2	1			T55	2		-	-		-	-