Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1358

1

T1

2

T15

10

T16

5

auto[1]

1361

1

T1

2

T15

7

T16

6

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

683

1

T15

17

T16

11

T19

32

auto[1]

2036

1

T1

4

T18

2

T66

7

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2445

1

T1

4

T15

7

T16

5

auto[1]

274

1

T15

10

T16

6

T19

12

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	540	1			T1	1		T15	3		T16	2
valid[1]	548	1			T1	1		T15	6		T16	3
valid[2]	517	1			T1	1		T15	4		T16	3
valid[3]	546	1			T15	2		T16	1		T18	1
valid[4]	568	1			T1	1		T15	2		T16	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	32	1			T15	1		T19	2		T393	2
auto[0]	auto[0]	valid[0]	auto[1]	205	1			T18	1		T66	2		T67	2
auto[0]	auto[0]	valid[1]	auto[0]	45	1			T15	2		T16	1		T19	1
auto[0]	auto[0]	valid[1]	auto[1]	218	1			T67	1		T112	1		T113	2
auto[0]	auto[0]	valid[2]	auto[0]	40	1			T16	1		T19	2		T410	1
auto[0]	auto[0]	valid[2]	auto[1]	179	1			T1	1		T66	1		T112	2
auto[0]	auto[0]	valid[3]	auto[0]	40	1			T15	1		T19	2		T65	1
auto[0]	auto[0]	valid[3]	auto[1]	202	1			T18	1		T66	1		T67	3
auto[0]	auto[0]	valid[4]	auto[0]	47	1			T15	1		T16	1		T109	1
auto[0]	auto[0]	valid[4]	auto[1]	207	1			T1	1		T66	1		T67	3
auto[0]	auto[1]	valid[0]	auto[0]	54	1			T19	1		T109	1		T110	2
auto[0]	auto[1]	valid[0]	auto[1]	197	1			T1	1		T67	1		T112	1
auto[0]	auto[1]	valid[1]	auto[0]	28	1			T19	2		T393	1		T387	1
auto[0]	auto[1]	valid[1]	auto[1]	200	1			T1	1		T112	1		T113	3
auto[0]	auto[1]	valid[2]	auto[0]	54	1			T15	1		T16	1		T19	3
auto[0]	auto[1]	valid[2]	auto[1]	192	1			T66	1		T112	2		T113	2
auto[0]	auto[1]	valid[3]	auto[0]	37	1			T15	1		T16	1		T19	4
auto[0]	auto[1]	valid[3]	auto[1]	215	1			T67	4		T112	1		T113	1
auto[0]	auto[1]	valid[4]	auto[0]	32	1			T19	3		T390	2		T389	1
auto[0]	auto[1]	valid[4]	auto[1]	221	1			T66	1		T67	3		T112	2
auto[1]	auto[0]	valid[0]	auto[0]	30	1			T15	1		T16	2		T109	1
auto[1]	auto[0]	valid[1]	auto[0]	31	1			T15	3		T65	1		T109	2
auto[1]	auto[0]	valid[2]	auto[0]	30	1			T15	1		T19	1		T69	1
auto[1]	auto[0]	valid[3]	auto[0]	24	1			T19	2		T387	2		T398	2
auto[1]	auto[0]	valid[4]	auto[0]	28	1			T19	3		T65	1		T390	1
auto[1]	auto[1]	valid[0]	auto[0]	22	1			T15	1		T19	1		T109	2
auto[1]	auto[1]	valid[1]	auto[0]	26	1			T15	1		T16	2		T19	1
auto[1]	auto[1]	valid[2]	auto[0]	22	1			T15	2		T16	1		T19	1
auto[1]	auto[1]	valid[3]	auto[0]	28	1			T19	1		T109	1		T393	1
auto[1]	auto[1]	valid[4]	auto[0]	33	1			T15	1		T16	1		T19	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal