Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17877

1

T15

336

T16

238

T17

17

auto[1]

19032

1

T1

49

T15

41

T16

43

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30279

1

T1

49

T15

234

T16

178

auto[1]

6630

1

T15

143

T16

103

T17

11

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	19065	1			T1	19		T15	205		T16	151
others[1]	3123	1			T1	3		T15	25		T16	19
others[2]	3151	1			T1	9		T15	34		T16	27
others[3]	3550	1			T1	8		T15	25		T16	19
interest[1]	2046	1			T1	3		T15	18		T16	14
interest[4]	12605	1			T1	12		T15	137		T16	94
interest[64]	5974	1			T1	7		T15	70		T16	51

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	5687	1			T15	108		T16	70		T17	3
auto[0]	auto[0]	others[1]	966	1			T15	12		T16	8		T17	2
auto[0]	auto[0]	others[2]	969	1			T15	13		T16	12		T17	1
auto[0]	auto[0]	others[3]	1104	1			T15	12		T16	14		T19	43
auto[0]	auto[0]	interest[1]	648	1			T15	11		T16	8		T19	32
auto[0]	auto[0]	interest[4]	3700	1			T15	69		T16	44		T17	3
auto[0]	auto[0]	interest[64]	1873	1			T15	37		T16	23		T19	66
auto[0]	auto[1]	others[0]	9992	1			T1	19		T15	20		T16	25
auto[0]	auto[1]	others[1]	1587	1			T1	3		T15	5		T16	4
auto[0]	auto[1]	others[2]	1587	1			T1	9		T15	3		T16	4
auto[0]	auto[1]	others[3]	1838	1			T1	8		T15	4		T16	2
auto[0]	auto[1]	interest[1]	1025	1			T1	3		T16	2		T18	2
auto[0]	auto[1]	interest[4]	6704	1			T1	12		T15	11		T16	16
auto[0]	auto[1]	interest[64]	3003	1			T1	7		T15	9		T16	6
auto[1]	auto[0]	others[0]	3386	1			T15	77		T16	56		T17	3
auto[1]	auto[0]	others[1]	570	1			T15	8		T16	7		T19	12
auto[1]	auto[0]	others[2]	595	1			T15	18		T16	11		T17	1
auto[1]	auto[0]	others[3]	608	1			T15	9		T16	3		T17	5
auto[1]	auto[0]	interest[1]	373	1			T15	7		T16	4		T17	1
auto[1]	auto[0]	interest[4]	2201	1			T15	57		T16	34		T17	2
auto[1]	auto[0]	interest[64]	1098	1			T15	24		T16	22		T17	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal