Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	482	1			T2	11		T34	18		T41	8
all_values[1]	482	1			T2	11		T34	18		T41	8
all_values[2]	482	1			T2	11		T34	18		T41	8
all_values[3]	482	1			T2	11		T34	18		T41	8
all_values[4]	482	1			T2	11		T34	18		T41	8
all_values[5]	482	1			T2	11		T34	18		T41	8
all_values[6]	482	1			T2	11		T34	18		T41	8
all_values[7]	482	1			T2	11		T34	18		T41	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2079

1

T2

40

T34

74

T41

32

auto[1]

1777

1

T2

48

T34

70

T41

32

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1544

1

T2

41

T34

45

T41

27

auto[1]

2312

1

T2

47

T34

99

T41

37

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2209

1

T2

53

T34

81

T41

38

auto[1]

1647

1

T2

35

T34

63

T41

26

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	112	1			T2	1		T34	4		T41	3
all_values[0]	auto[0]	auto[0]	auto[1]	49	1			T2	2		T34	2		T41	1
all_values[0]	auto[0]	auto[1]	auto[0]	80	1			T2	1		T34	2		T41	2
all_values[0]	auto[0]	auto[1]	auto[1]	36	1			T34	2		T40	4		T173	1
all_values[0]	auto[1]	auto[0]	auto[1]	101	1			T2	5		T34	1		T41	2
all_values[0]	auto[1]	auto[1]	auto[1]	104	1			T2	2		T34	7		T40	8
all_values[1]	auto[0]	auto[0]	auto[0]	102	1			T2	2		T34	4		T41	1
all_values[1]	auto[0]	auto[0]	auto[1]	52	1			T2	2		T34	6		T40	4
all_values[1]	auto[0]	auto[1]	auto[0]	78	1			T2	1		T34	3		T41	1
all_values[1]	auto[0]	auto[1]	auto[1]	42	1			T2	2		T34	1		T41	1
all_values[1]	auto[1]	auto[0]	auto[1]	107	1			T2	1		T34	3		T41	1
all_values[1]	auto[1]	auto[1]	auto[1]	101	1			T2	3		T34	1		T41	4
all_values[2]	auto[0]	auto[0]	auto[0]	100	1			T2	1		T41	2		T40	8
all_values[2]	auto[0]	auto[0]	auto[1]	50	1			T34	1		T40	2		T360	2
all_values[2]	auto[0]	auto[1]	auto[0]	80	1			T2	4		T34	2		T40	2
all_values[2]	auto[0]	auto[1]	auto[1]	34	1			T2	2		T34	4		T41	1
all_values[2]	auto[1]	auto[0]	auto[1]	121	1			T2	2		T34	3		T41	4
all_values[2]	auto[1]	auto[1]	auto[1]	97	1			T2	2		T34	8		T41	1
all_values[3]	auto[0]	auto[0]	auto[0]	100	1			T2	6		T34	3		T41	3
all_values[3]	auto[0]	auto[0]	auto[1]	52	1			T2	1		T34	5		T41	1
all_values[3]	auto[0]	auto[1]	auto[0]	80	1			T2	1		T34	1		T41	1
all_values[3]	auto[0]	auto[1]	auto[1]	49	1			T34	3		T41	1		T40	2
all_values[3]	auto[1]	auto[0]	auto[1]	123	1			T2	1		T34	5		T41	1
all_values[3]	auto[1]	auto[1]	auto[1]	78	1			T2	2		T34	1		T41	1
all_values[4]	auto[0]	auto[0]	auto[0]	97	1			T2	5		T34	1		T41	2
all_values[4]	auto[0]	auto[0]	auto[1]	44	1			T34	4		T41	3		T40	2
all_values[4]	auto[0]	auto[1]	auto[0]	73	1			T2	2		T34	1		T40	2
all_values[4]	auto[0]	auto[1]	auto[1]	60	1			T2	1		T34	3		T40	2
all_values[4]	auto[1]	auto[0]	auto[1]	104	1			T34	5		T41	2		T40	9
all_values[4]	auto[1]	auto[1]	auto[1]	104	1			T2	3		T34	4		T41	1
all_values[5]	auto[0]	auto[0]	auto[0]	137	1			T2	4		T34	5		T41	1
all_values[5]	auto[0]	auto[1]	auto[0]	135	1			T2	3		T34	7		T41	4
all_values[5]	auto[1]	auto[0]	auto[1]	112	1			T2	2		T34	5		T41	1
all_values[5]	auto[1]	auto[1]	auto[1]	98	1			T2	2		T34	1		T41	2
all_values[6]	auto[0]	auto[0]	auto[0]	92	1			T2	2		T34	2		T40	4
all_values[6]	auto[0]	auto[0]	auto[1]	52	1			T41	1		T40	4		T172	4
all_values[6]	auto[0]	auto[1]	auto[0]	89	1			T2	4		T34	1		T41	3
all_values[6]	auto[0]	auto[1]	auto[1]	38	1			T2	1		T34	2		T40	2
all_values[6]	auto[1]	auto[0]	auto[1]	107	1			T2	1		T34	6		T41	1
all_values[6]	auto[1]	auto[1]	auto[1]	104	1			T2	3		T34	7		T41	3
all_values[7]	auto[0]	auto[0]	auto[0]	110	1			T2	1		T34	7		T41	1
all_values[7]	auto[0]	auto[0]	auto[1]	57	1			T40	2		T360	4		T172	5
all_values[7]	auto[0]	auto[1]	auto[0]	79	1			T2	3		T34	2		T41	3
all_values[7]	auto[0]	auto[1]	auto[1]	50	1			T2	1		T34	3		T41	2
all_values[7]	auto[1]	auto[0]	auto[1]	98	1			T2	1		T34	2		T41	1
all_values[7]	auto[1]	auto[1]	auto[1]	88	1			T2	5		T34	4		T41	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal