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back
LINE 63
EXPRESSION (reg_we && ((!addrmiss)))
---1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T38,T121,T39 |
| 1 | 1 | Covered | T1,T2,T4 |
LINE 75
EXPRESSION (intg_err || reg_we_err)
----1--- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T50,T51,T52 |
| 1 | 0 | Covered | T38,T39,T125 |
LINE 82
EXPRESSION (err_q | intg_err | reg_we_err)
--1-- ----2--- -----3----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T50,T51,T52 |
| 0 | 1 | 0 | Covered | T38,T39,T125 |
| 1 | 0 | 0 | Covered | T50,T51,T52 |
LINE 132
EXPRESSION ((tl_i.a_address[(AW - 1):0] inside {[4096:7487]}) ? 2'b0 : ((tl_i.a_address[(AW - 1):0] inside {[7680:8127]}) ? 2'b1 : 2'd2))
------------------------1------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 132
SUB-EXPRESSION ((tl_i.a_address[(AW - 1):0] inside {[7680:8127]}) ? 2'b1 : 2'd2)
------------------------1------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 171
EXPRESSION (addrmiss | wr_err | intg_err)
----1--- ---2-- ----3---
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T38,T39,T125 |
| 0 | 1 | 0 | Covered | T121,T123,T124 |
| 1 | 0 | 0 | Covered | T121,T124,T126 |
LINE 19465
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_INTR_STATE_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 19466
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_INTR_ENABLE_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T15,T9 |
LINE 19467
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_INTR_TEST_OFFSET)
------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T15 |
LINE 19468
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_ALERT_TEST_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T15,T10,T30 |
LINE 19469
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CONTROL_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T15 |
LINE 19470
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CFG_OFFSET)
---------------------------1---------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T15,T5 |
LINE 19471
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_STATUS_OFFSET)
-----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T15,T10 |
LINE 19472
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_INTERCEPT_EN_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T15,T9 |
LINE 19473
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_ADDR_MODE_OFFSET)
------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T15 |
LINE 19474
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_LAST_READ_ADDR_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T15,T5 |
LINE 19475
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_FLASH_STATUS_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T15 |
LINE 19476
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_JEDEC_CC_OFFSET)
------------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T15 |
LINE 19477
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_JEDEC_ID_OFFSET)
------------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T15 |
LINE 19478
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_READ_THRESHOLD_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T15 |
LINE 19479
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_MAILBOX_ADDR_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T15 |
LINE 19480
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_UPLOAD_STATUS_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T10,T88,T73 |
LINE 19481
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_UPLOAD_STATUS2_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T15,T9,T10 |
LINE 19482
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_UPLOAD_CMDFIFO_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T15,T10,T88 |
LINE 19483
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_UPLOAD_ADDRFIFO_OFFSET)
---------------------------------1---------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T15,T9 |
LINE 19484
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_FILTER_0_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T4,T7 |
LINE 19485
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_FILTER_1_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T15 |
LINE 19486
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_FILTER_2_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T5 |
LINE 19487
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_FILTER_3_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T15 |
LINE 19488
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_FILTER_4_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T15 |
LINE 19489
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_FILTER_5_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T15 |
LINE 19490
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_FILTER_6_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T15 |
LINE 19491
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_FILTER_7_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T15 |
LINE 19492
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_ADDR_SWAP_MASK_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T15 |
LINE 19493
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_ADDR_SWAP_DATA_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T15 |
LINE 19494
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_PAYLOAD_SWAP_MASK_OFFSET)
----------------------------------1----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T15 |
LINE 19495
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_PAYLOAD_SWAP_DATA_OFFSET)
----------------------------------1----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T15 |
LINE 19496
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_0_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T15 |
LINE 19497
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_1_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T15 |
LINE 19498
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_2_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T15 |
LINE 19499
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_3_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T15 |
LINE 19500
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_4_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T7 |
LINE 19501
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_5_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T15 |
LINE 19502
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_6_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T15 |
LINE 19503
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_7_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T15 |
LINE 19504
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_8_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T15 |
LINE 19505
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_9_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T15 |
LINE 19506
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_10_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T15 |
LINE 19507
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_11_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T15 |
LINE 19508
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_12_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T15 |
LINE 19509
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_13_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T15 |
LINE 19510
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_14_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T15 |
LINE 19511
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_15_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T15 |
LINE 19512
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_16_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T15 |
LINE 19513
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_17_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T15 |
LINE 19514
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_18_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T15 |
LINE 19515
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_19_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T15 |
LINE 19516
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_20_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T7 |
LINE 19517
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_21_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T15 |
LINE 19518
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_22_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T15 |
LINE 19519
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_23_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T7,T15 |
LINE 19520
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_EN4B_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T15,T10,T88 |
LINE 19521
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_EX4B_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T15,T9,T10 |
LINE 19522
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_WREN_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T15,T10,T88 |
LINE 19523
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_WRDI_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T15,T9,T10 |
LINE 19524
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_CAP_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T10,T88,T127 |
LINE 19525
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_CFG_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T15,T10 |
LINE 19526
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_STATUS_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T15,T10 |
LINE 19527
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_ACCESS_0_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T15,T10 |
LINE 19528
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_ACCESS_1_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T15,T10 |
LINE 19529
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_STS_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T15,T10 |
LINE 19530
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_INTF_CAPABILITY_OFFSET)
-----------------------------------1-----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T15 |
LINE 19531
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_INT_ENABLE_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T15 |
LINE 19532
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_INT_VECTOR_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T15,T10 |
LINE 19533
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_INT_STATUS_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T15,T10 |
LINE 19534
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_DID_VID_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T15,T10 |
LINE 19535
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_RID_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T15,T10 |
LINE 19536
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_CMD_ADDR_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T15,T10,T16 |
LINE 19537
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_READ_FIFO_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T15,T9 |
LINE 19540
EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 19540
SUB-EXPRESSION (reg_re || reg_we)
---1-- ---2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T4 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 19544
EXPRESSION
Number Term
1 reg_we &
2 ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[12] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[16] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[29] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[30] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[31] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[32] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[33] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[34] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[35] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[36] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[37] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[38] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[39] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[40] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[41] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[42] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[43] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[44] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[45] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[46] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[47] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[48] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[49] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[50] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[51] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[52] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[53] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[54] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[55] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[56] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[57] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[58] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[59] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[60] & ((|(4'b1 & (~reg_be))))) | (addr_hit[61] & ((|(4'b1 & (~reg_be))))) | (addr_hit[62] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[63] & ((|(4'b1 & (~reg_be))))) | (addr_hit[64] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[65] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[66] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[67] & ((|(4'b1 & (~reg_be))))) | (addr_hit[68] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[69] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[70] & ((|(4'b1 & (~reg_be))))) | (addr_hit[71] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[72] & ((|(4'b1111 & (~reg_be)))))))
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T3,T4 |
| 1 | 0 | Covered | T1,T2,T4 |
| 1 | 1 | Covered | T121,T123,T124 |
LINE 19544
SUB-EXPRESSION
Number Term
1 (addr_hit[0] & ((|(4'b1 & (~reg_be))))) |
2 (addr_hit[1] & ((|(4'b1 & (~reg_be))))) |
3 (addr_hit[2] & ((|(4'b1 & (~reg_be))))) |
4 (addr_hit[3] & ((|(4'b1 & (~reg_be))))) |
5 (addr_hit[4] & ((|(4'b1 & (~reg_be))))) |
6 (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) |
7 (addr_hit[6] & ((|(4'b1 & (~reg_be))))) |
8 (addr_hit[7] & ((|(4'b1 & (~reg_be))))) |
9 (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) |
10 (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) |
11 (addr_hit[10] & ((|(4'b0111 & (~reg_be))))) |
12 (addr_hit[11] & ((|(4'b0011 & (~reg_be))))) |
13 (addr_hit[12] & ((|(4'b0111 & (~reg_be))))) |
14 (addr_hit[13] & ((|(4'b0011 & (~reg_be))))) |
15 (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) |
16 (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) |
17 (addr_hit[16] & ((|(4'b0111 & (~reg_be))))) |
18 (addr_hit[17] & ((|(4'b0011 & (~reg_be))))) |
19 (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) |
20 (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) |
21 (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) |
22 (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) |
23 (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) |
24 (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) |
25 (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) |
26 (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) |
27 (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) |
28 (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) |
29 (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) |
30 (addr_hit[29] & ((|(4'b1111 & (~reg_be))))) |
31 (addr_hit[30] & ((|(4'b1111 & (~reg_be))))) |
32 (addr_hit[31] & ((|(4'b1111 & (~reg_be))))) |
33 (addr_hit[32] & ((|(4'b1111 & (~reg_be))))) |
34 (addr_hit[33] & ((|(4'b1111 & (~reg_be))))) |
35 (addr_hit[34] & ((|(4'b1111 & (~reg_be))))) |
36 (addr_hit[35] & ((|(4'b1111 & (~reg_be))))) |
37 (addr_hit[36] & ((|(4'b1111 & (~reg_be))))) |
38 (addr_hit[37] & ((|(4'b1111 & (~reg_be))))) |
39 (addr_hit[38] & ((|(4'b1111 & (~reg_be))))) |
40 (addr_hit[39] & ((|(4'b1111 & (~reg_be))))) |
41 (addr_hit[40] & ((|(4'b1111 & (~reg_be))))) |
42 (addr_hit[41] & ((|(4'b1111 & (~reg_be))))) |
43 (addr_hit[42] & ((|(4'b1111 & (~reg_be))))) |
44 (addr_hit[43] & ((|(4'b1111 & (~reg_be))))) |
45 (addr_hit[44] & ((|(4'b1111 & (~reg_be))))) |
46 (addr_hit[45] & ((|(4'b1111 & (~reg_be))))) |
47 (addr_hit[46] & ((|(4'b1111 & (~reg_be))))) |
48 (addr_hit[47] & ((|(4'b1111 & (~reg_be))))) |
49 (addr_hit[48] & ((|(4'b1111 & (~reg_be))))) |
50 (addr_hit[49] & ((|(4'b1111 & (~reg_be))))) |
51 (addr_hit[50] & ((|(4'b1111 & (~reg_be))))) |
52 (addr_hit[51] & ((|(4'b1111 & (~reg_be))))) |
53 (addr_hit[52] & ((|(4'b1111 & (~reg_be))))) |
54 (addr_hit[53] & ((|(4'b1111 & (~reg_be))))) |
55 (addr_hit[54] & ((|(4'b1111 & (~reg_be))))) |
56 (addr_hit[55] & ((|(4'b1111 & (~reg_be))))) |
57 (addr_hit[56] & ((|(4'b1111 & (~reg_be))))) |
58 (addr_hit[57] & ((|(4'b1111 & (~reg_be))))) |
59 (addr_hit[58] & ((|(4'b1111 & (~reg_be))))) |
60 (addr_hit[59] & ((|(4'b0111 & (~reg_be))))) |
61 (addr_hit[60] & ((|(4'b1 & (~reg_be))))) |
62 (addr_hit[61] & ((|(4'b1 & (~reg_be))))) |
63 (addr_hit[62] & ((|(4'b1111 & (~reg_be))))) |
64 (addr_hit[63] & ((|(4'b1 & (~reg_be))))) |
65 (addr_hit[64] & ((|(4'b1111 & (~reg_be))))) |
66 (addr_hit[65] & ((|(4'b1111 & (~reg_be))))) |
67 (addr_hit[66] & ((|(4'b1111 & (~reg_be))))) |
68 (addr_hit[67] & ((|(4'b1 & (~reg_be))))) |
69 (addr_hit[68] & ((|(4'b1111 & (~reg_be))))) |
70 (addr_hit[69] & ((|(4'b1111 & (~reg_be))))) |
71 (addr_hit[70] & ((|(4'b1 & (~reg_be))))) |
72 (addr_hit[71] & ((|(4'b1111 & (~reg_be))))) |
73 (addr_hit[72] & ((|(4'b1111 & (~reg_be))))))
| Sensitive Expression == 1 | Status | Tests |
|---|
| ALL ZEROS | Covered | T1,T2,T3 |
| 73 (addr_hit[72] & ((|(4'... | Covered | T3,T9,T10 |
| 72 (addr_hit[71] & ((|(4'... | Covered | T15,T10,T16 |
| 71 (addr_hit[70] & ((|(4'... | Covered | T15,T10,T88 |
| 70 (addr_hit[69] & ((|(4'... | Covered | T15,T10,T88 |
| 69 (addr_hit[68] & ((|(4'... | Covered | T15,T10,T88 |
| 68 (addr_hit[67] & ((|(4'... | Covered | T10,T88,T127 |
| 67 (addr_hit[66] & ((|(4'... | Covered | T3,T15,T9 |
| 66 (addr_hit[65] & ((|(4'... | Covered | T3,T15,T10 |
| 65 (addr_hit[64] & ((|(4'... | Covered | T15,T10,T88 |
| 64 (addr_hit[63] & ((|(4'... | Covered | T15,T88,T73 |
| 63 (addr_hit[62] & ((|(4'... | Covered | T15,T10,T88 |
| 62 (addr_hit[61] & ((|(4'... | Covered | T15,T10,T88 |
| 61 (addr_hit[60] & ((|(4'... | Covered | T88,T49,T127 |
| 60 (addr_hit[59] & ((|(4'... | Covered | T10,T88,T127 |
| 59 (addr_hit[58] & ((|(4'... | Covered | T15,T9,T10 |
| 58 (addr_hit[57] & ((|(4'... | Covered | T15,T10,T88 |
| 57 (addr_hit[56] & ((|(4'... | Covered | T15,T9,T10 |
| 56 (addr_hit[55] & ((|(4'... | Covered | T15,T10,T88 |
| 55 (addr_hit[54] & ((|(4'... | Covered | T15,T10,T88 |
| 54 (addr_hit[53] & ((|(4'... | Covered | T15,T9,T10 |
| 53 (addr_hit[52] & ((|(4'... | Covered | T15,T10,T88 |
| 52 (addr_hit[51] & ((|(4'... | Covered | T2,T15,T10 |
| 51 (addr_hit[50] & ((|(4'... | Covered | T15,T10,T88 |
| 50 (addr_hit[49] & ((|(4'... | Covered | T15,T9,T10 |
| 49 (addr_hit[48] & ((|(4'... | Covered | T10,T88,T49 |
| 48 (addr_hit[47] & ((|(4'... | Covered | T15,T10,T88 |
| 47 (addr_hit[46] & ((|(4'... | Covered | T15,T10,T88 |
| 46 (addr_hit[45] & ((|(4'... | Covered | T15,T10,T88 |
| 45 (addr_hit[44] & ((|(4'... | Covered | T15,T10,T88 |
| 44 (addr_hit[43] & ((|(4'... | Covered | T15,T10,T88 |
| 43 (addr_hit[42] & ((|(4'... | Covered | T15,T10,T88 |
| 42 (addr_hit[41] & ((|(4'... | Covered | T15,T10,T88 |
| 41 (addr_hit[40] & ((|(4'... | Covered | T15,T88,T49 |
| 40 (addr_hit[39] & ((|(4'... | Covered | T15,T9,T10 |
| 39 (addr_hit[38] & ((|(4'... | Covered | T15,T10,T88 |
| 38 (addr_hit[37] & ((|(4'... | Covered | T15,T88,T49 |
| 37 (addr_hit[36] & ((|(4'... | Covered | T15,T10,T88 |
| 36 (addr_hit[35] & ((|(4'... | Covered | T15,T10,T88 |
| 35 (addr_hit[34] & ((|(4'... | Covered | T15,T10,T88 |
| 34 (addr_hit[33] & ((|(4'... | Covered | T15,T10,T88 |
| 33 (addr_hit[32] & ((|(4'... | Covered | T15,T10,T88 |
| 32 (addr_hit[31] & ((|(4'... | Covered | T15,T9,T10 |
| 31 (addr_hit[30] & ((|(4'... | Covered | T15,T9,T10 |
| 30 (addr_hit[29] & ((|(4'... | Covered | T15,T10,T88 |
| 29 (addr_hit[28] & ((|(4'... | Covered | T15,T10,T88 |
| 28 (addr_hit[27] & ((|(4'... | Covered | T15,T10,T88 |
| 27 (addr_hit[26] & ((|(4'... | Covered | T15,T10,T88 |
| 26 (addr_hit[25] & ((|(4'... | Covered | T15,T9,T10 |
| 25 (addr_hit[24] & ((|(4'... | Covered | T15,T9,T10 |
| 24 (addr_hit[23] & ((|(4'... | Covered | T15,T10,T127 |
| 23 (addr_hit[22] & ((|(4'... | Covered | T15,T10,T88 |
| 22 (addr_hit[21] & ((|(4'... | Covered | T10,T88,T49 |
| 21 (addr_hit[20] & ((|(4'... | Covered | T15,T10,T88 |
| 20 (addr_hit[19] & ((|(4'... | Covered | T3,T10,T88 |
| 19 (addr_hit[18] & ((|(4'... | Covered | T2,T15,T9 |
| 18 (addr_hit[17] & ((|(4'... | Covered | T15,T10,T88 |
| 17 (addr_hit[16] & ((|(4'... | Covered | T15,T9,T10 |
| 16 (addr_hit[15] & ((|(4'... | Covered | T10,T88,T73 |
| 15 (addr_hit[14] & ((|(4'... | Covered | T15,T10,T88 |
| 14 (addr_hit[13] & ((|(4'... | Covered | T15,T10,T88 |
| 13 (addr_hit[12] & ((|(4'... | Covered | T15,T10,T88 |
| 12 (addr_hit[11] & ((|(4'... | Covered | T15,T10,T88 |
| 11 (addr_hit[10] & ((|(4'... | Covered | T4,T15,T9 |
| 10 (addr_hit[9] & ((|(4'b... | Covered | T4,T15,T5 |
| 9 (addr_hit[8] & ((|(4'b... | Covered | T15,T9,T10 |
| 8 (addr_hit[7] & ((|(4'b... | Covered | T15,T88,T73 |
| 7 (addr_hit[6] & ((|(4'b... | Covered | T15,T10,T88 |
| 6 (addr_hit[5] & ((|(4'b... | Covered | T15,T10,T88 |
| 5 (addr_hit[4] & ((|(4'b... | Covered | T15,T10,T88 |
| 4 (addr_hit[3] & ((|(4'b... | Covered | T15,T10,T88 |
| 3 (addr_hit[2] & ((|(4'b... | Covered | T2,T3,T15 |
| 2 (addr_hit[1] & ((|(4'b... | Covered | T2,T15,T88 |
| 1 (addr_hit[0] & ((|(4'b... | Covered | T2,T4,T15 |
LINE 19544
SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T4,T15 |
LINE 19544
SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T9,T88 |
| 1 | 1 | Covered | T2,T15,T88 |
LINE 19544
SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T15,T88 |
| 1 | 1 | Covered | T2,T3,T15 |
LINE 19544
SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T15,T10,T30 |
| 1 | 1 | Covered | T15,T10,T88 |
LINE 19544
SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T7,T5 |
| 1 | 1 | Covered | T15,T10,T88 |
LINE 19544
SUB-EXPRESSION (addr_hit[5] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T5,T9 |
| 1 | 1 | Covered | T15,T10,T88 |
LINE 19544
SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T15,T20 |
| 1 | 1 | Covered | T15,T10,T88 |
LINE 19544
SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T15,T9 |
| 1 | 1 | Covered | T15,T88,T73 |
LINE 19544
SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T7,T5 |
| 1 | 1 | Covered | T15,T9,T10 |
LINE 19544
SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T4,T15,T5 |
LINE 19544
SUB-EXPRESSION (addr_hit[10] & ((|(4'b0111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T7,T5 |
| 1 | 1 | Covered | T4,T15,T9 |
LINE 19544
SUB-EXPRESSION (addr_hit[11] & ((|(4'b0011 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T7,T15 |
| 1 | 1 | Covered | T15,T10,T88 |
LINE 19544
SUB-EXPRESSION (addr_hit[12] & ((|(4'b0111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T7,T5 |
| 1 | 1 | Covered | T15,T10,T88 |
LINE 19544
SUB-EXPRESSION (addr_hit[13] & ((|(4'b0011 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T7,T15 |
| 1 | 1 | Covered | T15,T10,T88 |
LINE 19544
SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T7,T5 |
| 1 | 1 | Covered | T15,T10,T88 |
LINE 19544
SUB-EXPRESSION (addr_hit[15] & ((|(4'b0011 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T88,T127,T128 |
| 1 | 1 | Covered | T10,T88,T73 |
LINE 19544
SUB-EXPRESSION (addr_hit[16] & ((|(4'b0111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T15,T88,T127 |
| 1 | 1 | Covered | T15,T9,T10 |
LINE 19544
SUB-EXPRESSION (addr_hit[17] & ((|(4'b0011 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T15,T88,T127 |
| 1 | 1 | Covered | T15,T10,T88 |
LINE 19544
SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T15,T127,T129 |
| 1 | 1 | Covered | T2,T15,T9 |
LINE 19544
SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T7,T15 |
| 1 | 1 | Covered | T3,T10,T88 |
LINE 19544
SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T7,T15 |
| 1 | 1 | Covered | T15,T10,T88 |
LINE 19544
SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T7,T5 |
| 1 | 1 | Covered | T10,T88,T49 |
LINE 19544
SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T7,T5 |
| 1 | 1 | Covered | T15,T10,T88 |
LINE 19544
SUB-EXPRESSION (addr_hit[23] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T7,T15 |
| 1 | 1 | Covered | T15,T10,T127 |
LINE 19544
SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T7,T5 |
| 1 | 1 | Covered | T15,T9,T10 |
LINE 19544
SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T7,T5 |
| 1 | 1 | Covered | T15,T9,T10 |
LINE 19544
SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T7,T5 |
| 1 | 1 | Covered | T15,T10,T88 |
LINE 19544
SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T7,T5 |
| 1 | 1 | Covered | T15,T10,T88 |
LINE 19544
SUB-EXPRESSION (addr_hit[28] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T7,T5 |
| 1 | 1 | Covered | T15,T10,T88 |
LINE 19544
SUB-EXPRESSION (addr_hit[29] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T7,T5 |
| 1 | 1 | Covered | T15,T10,T88 |
LINE 19544
SUB-EXPRESSION (addr_hit[30] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T7,T5 |
| 1 | 1 | Covered | T15,T9,T10 |
LINE 19544
SUB-EXPRESSION (addr_hit[31] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T7,T5 |
| 1 | 1 | Covered | T15,T9,T10 |
LINE 19544
SUB-EXPRESSION (addr_hit[32] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T7,T5 |
| 1 | 1 | Covered | T15,T10,T88 |
LINE 19544
SUB-EXPRESSION (addr_hit[33] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T7,T5 |
| 1 | 1 | Covered | T15,T10,T88 |
LINE 19544
SUB-EXPRESSION (addr_hit[34] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T7,T5 |
| 1 | 1 | Covered | T15,T10,T88 |
LINE 19544
SUB-EXPRESSION (addr_hit[35] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T4,T7 |
| 1 | 1 | Covered | T15,T10,T88 |
LINE 19544
SUB-EXPRESSION (addr_hit[36] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T7,T5 |
| 1 | 1 | Covered | T15,T10,T88 |
LINE 19544
SUB-EXPRESSION (addr_hit[37] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T7,T15 |
| 1 | 1 | Covered | T15,T88,T49 |
LINE 19544
SUB-EXPRESSION (addr_hit[38] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T7,T15 |
| 1 | 1 | Covered | T15,T10,T88 |
LINE 19544
SUB-EXPRESSION (addr_hit[39] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T7,T5 |
| 1 | 1 | Covered | T15,T9,T10 |
LINE 19544
SUB-EXPRESSION (addr_hit[40] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T7,T5 |
| 1 | 1 | Covered | T15,T88,T49 |
LINE 19544
SUB-EXPRESSION (addr_hit[41] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T7,T5 |
| 1 | 1 | Covered | T15,T10,T88 |
LINE 19544
SUB-EXPRESSION (addr_hit[42] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T7,T5 |
| 1 | 1 | Covered | T15,T10,T88 |
LINE 19544
SUB-EXPRESSION (addr_hit[43] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T7,T5 |
| 1 | 1 | Covered | T15,T10,T88 |
LINE 19544
SUB-EXPRESSION (addr_hit[44] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T7,T5 |
| 1 | 1 | Covered | T15,T10,T88 |
LINE 19544
SUB-EXPRESSION (addr_hit[45] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T7,T5 |
| 1 | 1 | Covered | T15,T10,T88 |
LINE 19544
SUB-EXPRESSION (addr_hit[46] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T7,T5 |
| 1 | 1 | Covered | T15,T10,T88 |
LINE 19544
SUB-EXPRESSION (addr_hit[47] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T7,T5 |
| 1 | 1 | Covered | T15,T10,T88 |
LINE 19544
SUB-EXPRESSION (addr_hit[48] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T7,T15 |
| 1 | 1 | Covered | T10,T88,T49 |