Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	287345	1			T1	14		T2	1		T3	1
all_values[1]	287345	1			T1	14		T2	1		T3	1
all_values[2]	287345	1			T1	14		T2	1		T3	1
all_values[3]	287345	1			T1	14		T2	1		T3	1
all_values[4]	287345	1			T1	14		T2	1		T3	1
all_values[5]	287345	1			T1	14		T2	1		T3	1
all_values[6]	287345	1			T1	14		T2	1		T3	1
all_values[7]	287345	1			T1	14		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2296715

1

T1

112

T2

8

T3

8

auto[1]

2045

1

T32

93

T33

24

T34

55

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2296868

1

T1

112

T2

8

T3

8

auto[1]

1892

1

T63

1

T64

4

T32

48

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	286980	1			T1	14		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	138	1			T32	6		T33	3		T34	4
all_values[0]	auto[1]	auto[0]	117	1			T32	4		T41	3		T354	1
all_values[0]	auto[1]	auto[1]	110	1			T32	3		T33	2		T34	2
all_values[1]	auto[0]	auto[0]	286978	1			T1	14		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	111	1			T33	6		T34	2		T41	5
all_values[1]	auto[1]	auto[0]	155	1			T32	9		T34	3		T41	7
all_values[1]	auto[1]	auto[1]	101	1			T32	7		T34	8		T41	4
all_values[2]	auto[0]	auto[0]	286985	1			T1	14		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	81	1			T32	3		T33	1		T34	2
all_values[2]	auto[1]	auto[0]	190	1			T32	13		T33	2		T34	3
all_values[2]	auto[1]	auto[1]	89	1			T32	2		T33	1		T34	3
all_values[3]	auto[0]	auto[0]	286954	1			T1	14		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	135	1			T32	1		T33	1		T96	5
all_values[3]	auto[1]	auto[0]	143	1			T32	6		T33	2		T34	3
all_values[3]	auto[1]	auto[1]	113	1			T32	8		T41	2		T174	2
all_values[4]	auto[0]	auto[0]	286977	1			T1	14		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	117	1			T32	5		T102	1		T33	1
all_values[4]	auto[1]	auto[0]	155	1			T32	10		T33	2		T34	5
all_values[4]	auto[1]	auto[1]	96	1			T32	2		T34	4		T41	3
all_values[5]	auto[0]	auto[0]	286751	1			T1	14		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	316	1			T63	1		T64	4		T32	2
all_values[5]	auto[1]	auto[0]	188	1			T32	14		T33	4		T34	5
all_values[5]	auto[1]	auto[1]	90	1			T32	1		T33	1		T34	3
all_values[6]	auto[0]	auto[0]	287000	1			T1	14		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	120	1			T32	3		T33	2		T34	5
all_values[6]	auto[1]	auto[0]	144	1			T32	2		T33	2		T34	3
all_values[6]	auto[1]	auto[1]	81	1			T33	1		T34	5		T41	1
all_values[7]	auto[0]	auto[0]	286988	1			T1	14		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	84	1			T32	2		T34	2		T41	2
all_values[7]	auto[1]	auto[0]	163	1			T32	9		T33	5		T34	7
all_values[7]	auto[1]	auto[1]	110	1			T32	3		T33	2		T34	1