Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
72.95	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	1	37	97.37
Crosses	84	32	52	61.90

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	1	1	50.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	28	20	41.67	100	1	1	0
cr_modeXdummyXnum_lanes	36	4	32	88.89	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	978	1			T7	10		T8	2		T9	4
auto[SpiFlashAddrCfg]	890	1			T1	5		T4	4		T5	6
auto[SpiFlashAddr3b]	895	1			T4	4		T7	10		T8	6
auto[SpiFlashAddr4b]	870	1			T1	4		T4	2		T5	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2807

1

T1

9

T4

10

T5

8

auto[1]

826

1

T7

28

T76

22

T77

16

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1831

1

T1

3

T4

6

T5

2

auto[1]

1802

1

T1

6

T4

4

T5

6

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1406	1			T4	4		T7	14		T8	4
values[1]	60	1			T77	2		T45	2		T74	4
values[2]	133	1			T7	4		T43	2		T82	4
values[3]	137	1			T4	2		T7	2		T8	2
values[4]	200	1			T5	6		T7	6		T8	2
values[5]	168	1			T5	2		T107	2		T202	4
values[6]	186	1			T107	2		T79	8		T82	6
values[7]	143	1			T7	2		T43	2		T82	2
values[8]	1200	1			T1	9		T4	4		T8	4

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3126

1

T4

10

T5

8

T7

28

auto[1]

507

1

T1

9

T101

16

T114

10

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

3537

1

T1

9

T4

10

T5

8

write

96

1

T71

4

T74

2

T72

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

1789

1

T1

9

T4

6

T5

8

valids[0x1]

1844

1

T4

4

T7

24

T8

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	164	1			T7	6		T8	2		T46	2
internal_process_ops[0x5a]	160	1			T4	4		T9	2		T12	2
internal_process_ops[0x05]	218	1			T43	2		T107	2		T197	2
internal_process_ops[0x35]	122	1			T43	4		T113	2		T44	4
internal_process_ops[0x15]	176	1			T7	4		T9	4		T107	2
internal_process_ops[0x03]	242	1			T7	4		T8	2		T114	2
internal_process_ops[0x0b]	250	1			T8	2		T101	1		T113	2
internal_process_ops[0x3b]	265	1			T4	4		T5	6		T8	2
internal_process_ops[0x6b]	310	1			T1	2		T4	2		T5	2
internal_process_ops[0xbb]	278	1			T1	4		T8	4		T12	2
internal_process_ops[0xeb]	266	1			T1	3		T197	2		T79	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3581

1

T1

9

T4

10

T5

8

auto[1]

52

1

T71

4

T73

10

T78

4

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_upload

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3633

1

T1

9

T4

10

T5

8

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	28	20	41.67	28
Automatically Generated Cross Bins	48	28	20	41.67	28
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Element holes

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[write]	*	[auto[0]]	[auto[1]]	--	--	4
[auto[0]]	[write]	*	[auto[1]]	[auto[0]]	--	--	4
[auto[1]]	[read]	*	[auto[1]]	[auto[0]]	--	--	4
[auto[1]]	[write]	*	*	*	--	--	16

Covered bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

762

1

T8

2

T9

4

T43

6

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

194

1

T7

10

T76

6

T77

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

512

1

T4

4

T5

6

T8

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

190

1

T76

4

T77

8

T71

8

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

540

1

T4

4

T8

6

T9

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

226

1

T7

10

T76

4

T77

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

442

1

T4

2

T5

2

T8

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

164

1

T7

8

T76

8

T193

8

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

14

1

T74

2

T72

2

T221

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

6

1

T71

4

T91

2

-

-

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2

1

T83

2

-

-

-

-

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

18

1

T73

4

T88

2

T291

8

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

14

1

T83

2

T293

4

T275

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

8

1

T73

6

T85

2

-

-

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

14

1

T185

2

T294

6

T295

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

20

1

T78

4

T86

6

T87

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

2

1

T296

2

-

-

-

-

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

168

1

T1

5

T101

4

T102

7

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

107

1

T101

5

T297

4

T298

6

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

230

1

T1

4

T101

7

T114

10

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	4	32	88.89	4

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Uncovered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[1]]	[valids[0x0]]	0	1	1
[auto[1]]	[values[1]]	[valids[0x0]]	0	1	1
[auto[1]]	[values[2]]	[valids[0x1]]	0	1	1
[auto[1]]	[values[6]]	[valids[0x1]]	0	1	1

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	286	1			T12	2		T28	4		T25	6
auto[0]	values[0]	valids[0x1]	1044	1			T4	4		T7	14		T8	4
auto[0]	values[1]	valids[0x1]	50	1			T77	2		T45	2		T74	4
auto[0]	values[2]	valids[0x0]	74	1			T43	2		T82	4		T80	4
auto[0]	values[2]	valids[0x1]	22	1			T7	4		T71	2		T81	2
auto[0]	values[3]	valids[0x0]	88	1			T4	2		T7	2		T12	2
auto[0]	values[3]	valids[0x1]	24	1			T8	2		T192	2		T79	4
auto[0]	values[4]	valids[0x0]	120	1			T5	6		T8	2		T93	4
auto[0]	values[4]	valids[0x1]	48	1			T7	6		T82	2		T238	2
auto[0]	values[5]	valids[0x0]	106	1			T5	2		T202	2		T196	2
auto[0]	values[5]	valids[0x1]	40	1			T107	2		T202	2		T84	2
auto[0]	values[6]	valids[0x0]	102	1			T107	2		T79	8		T238	10
auto[0]	values[6]	valids[0x1]	52	1			T82	6		T93	6		T253	2
auto[0]	values[7]	valids[0x0]	90	1			T7	2		T44	2		T71	2
auto[0]	values[7]	valids[0x1]	30	1			T43	2		T82	2		T77	2
auto[0]	values[8]	valids[0x0]	576	1			T4	4		T8	4		T9	2
auto[0]	values[8]	valids[0x1]	374	1			T9	2		T75	2		T107	2
auto[1]	values[0]	valids[0x0]	2	1			T299	2		-	-		-	-
auto[1]	values[0]	valids[0x1]	74	1			T114	2		T102	7		T300	2
auto[1]	values[1]	valids[0x1]	10	1			T301	3		T302	3		T303	4
auto[1]	values[2]	valids[0x0]	37	1			T297	4		T304	1		T305	8
auto[1]	values[3]	valids[0x0]	13	1			T300	4		T306	2		T307	7
auto[1]	values[3]	valids[0x1]	12	1			T306	6		T308	6		-	-
auto[1]	values[4]	valids[0x0]	28	1			T102	4		T309	3		T53	4
auto[1]	values[4]	valids[0x1]	4	1			T298	2		T310	2		-	-
auto[1]	values[5]	valids[0x0]	19	1			T304	3		T311	4		T312	3
auto[1]	values[5]	valids[0x1]	3	1			T313	3		-	-		-	-
auto[1]	values[6]	valids[0x0]	32	1			T314	3		T305	6		T306	1
auto[1]	values[7]	valids[0x0]	12	1			T298	8		T301	4		-	-
auto[1]	values[7]	valids[0x1]	11	1			T315	7		T306	4		-	-
auto[1]	values[8]	valids[0x0]	204	1			T1	9		T101	15		T114	8
auto[1]	values[8]	valids[0x1]	46	1			T101	1		T300	5		T316	7