Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
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Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
36.36 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv



Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 16 2 14 87.50
Crosses 72 54 18 25.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_busy_bit 2 1 1 50.00 100 1 1 2
cp_is_host_read 2 0 2 100.00 100 1 1 2
cp_other_status 8 0 8 100.00 100 1 1 8
cp_sw_read_while_csb_active 2 0 2 100.00 100 1 1 2
cp_wel_bit 2 1 1 50.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all_except_csb 64 48 16 25.00 100 1 1 0
cr_busyXwelXcsb 8 6 2 25.00 100 1 1 0


Summary for Variable cp_busy_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_busy_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1829467 1 T1 26357 T2 2354 T4 542



Summary for Variable cp_is_host_read

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_is_host_read

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1726655 1 T1 26357 T2 2354 T4 542
auto[1] 102812 1 T43 1030 T44 1546 T45 4396



Summary for Variable cp_other_status

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 8 0 8 100.00


Automatically Generated Bins for cp_other_status

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:524287] 435878 1 T1 958 T2 460 T4 111
auto[524288:1048575] 197622 1 T1 85 T2 111 T5 5632
auto[1048576:1572863] 181532 1 T1 5849 T4 59 T5 2415
auto[1572864:2097151] 218877 1 T1 9604 T2 904 T4 103
auto[2097152:2621439] 198324 1 T1 2806 T4 102 T5 2
auto[2621440:3145727] 207340 1 T4 50 T5 6379 T8 1165
auto[3145728:3670015] 196599 1 T1 3098 T4 117 T5 12465
auto[3670016:4194303] 193295 1 T1 3957 T2 879 T5 3298



Summary for Variable cp_sw_read_while_csb_active

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sw_read_while_csb_active

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 115669 1 T1 178 T2 94 T4 48
auto[1] 1713798 1 T1 26179 T2 2260 T4 494



Summary for Variable cp_wel_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_wel_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1829467 1 T1 26357 T2 2354 T4 542



Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 48 16 25.00 48


Automatically Generated Cross Bins for cr_all_except_csb

Element holes
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * * -- -- 16
[auto[1]] * * * -- -- 32


Covered bins
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0:524287] auto[0] 359845 1 T1 958 T2 460 T4 111
auto[0] auto[0] auto[0:524287] auto[1] 76033 1 T43 1030 T44 1546 T45 4396
auto[0] auto[0] auto[524288:1048575] auto[0] 190758 1 T1 85 T2 111 T5 5632
auto[0] auto[0] auto[524288:1048575] auto[1] 6864 1 T186 151 T47 1108 T99 266
auto[0] auto[0] auto[1048576:1572863] auto[0] 175958 1 T1 5849 T4 59 T5 2415
auto[0] auto[0] auto[1048576:1572863] auto[1] 5574 1 T186 264 T47 3634 T187 266
auto[0] auto[0] auto[1572864:2097151] auto[0] 215123 1 T1 9604 T2 904 T4 103
auto[0] auto[0] auto[1572864:2097151] auto[1] 3754 1 T111 257 T47 2984 T188 9
auto[0] auto[0] auto[2097152:2621439] auto[0] 196011 1 T1 2806 T4 102 T5 2
auto[0] auto[0] auto[2097152:2621439] auto[1] 2313 1 T47 504 T130 118 T189 1
auto[0] auto[0] auto[2621440:3145727] auto[0] 203680 1 T4 50 T5 6379 T8 1165
auto[0] auto[0] auto[2621440:3145727] auto[1] 3660 1 T106 250 T190 250 T191 3157
auto[0] auto[0] auto[3145728:3670015] auto[0] 193060 1 T1 3098 T4 117 T5 12465
auto[0] auto[0] auto[3145728:3670015] auto[1] 3539 1 T47 1367 T99 246 T130 123
auto[0] auto[0] auto[3670016:4194303] auto[0] 192220 1 T1 3957 T2 879 T5 3298
auto[0] auto[0] auto[3670016:4194303] auto[1] 1075 1 T186 248 T47 39 T130 1



Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 6 2 25.00 6


Automatically Generated Cross Bins for cr_busyXwelXcsb

Element holes
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * -- -- 2
[auto[1]] * * -- -- 4


Covered bins
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 115669 1 T1 178 T2 94 T4 48
auto[0] auto[0] auto[1] 1713798 1 T1 26179 T2 2260 T4 494

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