Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
75.34	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	36	92	71.88

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	36	92	71.88	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2300

1

T4

10

T5

8

T8

12

auto[1]

826

1

T7

28

T76

22

T77

16

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	358	1			T12	6		T75	2		T113	8
values[1]	488	1			T5	8		T7	28		T8	12
values[2]	400	1			T9	8		T193	18		T196	4
values[3]	346	1			T43	10		T192	4		T46	2
values[4]	364	1			T25	6		T79	28		T76	22
values[5]	262	1			T188	6		T221	12		T189	14
values[6]	442	1			T197	4		T110	10		T108	8
values[7]	466	1			T4	10		T28	4		T77	16

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	366	1			T5	8		T8	12		T75	2
values[1]	400	1			T26	6		T82	20		T44	12
values[2]	358	1			T12	6		T77	16		T194	4
values[3]	276	1			T43	10		T46	2		T76	22
values[4]	550	1			T107	18		T197	4		T110	10
values[5]	348	1			T9	8		T28	4		T113	8
values[6]	430	1			T4	10		T108	8		T27	14
values[7]	398	1			T7	28		T192	4		T285	8

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	36	92	71.88	36

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[2]]	[values[1]]	0	1	1
[auto[0]]	[values[3]]	[values[5]]	0	1	1
[auto[0]]	[values[4]]	[values[3]]	0	1	1
[auto[0]]	[values[4]]	[values[5]]	0	1	1
[auto[0]]	[values[5]]	[values[7]]	0	1	1
[auto[0]]	[values[6]]	[values[3]]	0	1	1
[auto[0]]	[values[7]]	[values[2]]	0	1	1
[auto[1]]	[values[0]]	[values[0]]	0	1	1
[auto[1]]	[values[0]]	[values[2]]	0	1	1
[auto[1]]	[values[0]]	[values[5] , values[6]]	--	--	2
[auto[1]]	[values[1]]	[values[3] , values[4] , values[5]]	--	--	3
[auto[1]]	[values[2]]	[values[4] , values[5] , values[6] , values[7]]	--	--	4
[auto[1]]	[values[3]]	[values[0]]	0	1	1
[auto[1]]	[values[3]]	[values[3]]	0	1	1
[auto[1]]	[values[3]]	[values[5]]	0	1	1
[auto[1]]	[values[4]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[4]]	[values[5]]	0	1	1
[auto[1]]	[values[5]]	[values[0] , values[1] , values[2] , values[3] , values[4]]	--	--	5
[auto[1]]	[values[5]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[6]]	[values[1]]	0	1	1
[auto[1]]	[values[6]]	[values[5]]	0	1	1
[auto[1]]	[values[7]]	[values[0]]	0	1	1
[auto[1]]	[values[7]]	[values[3] , values[4]]	--	--	2

Covered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	2	1			T75	2		-	-		-	-
auto[0]	values[0]	values[1]	34	1			T98	10		T242	24		-	-
auto[0]	values[0]	values[2]	18	1			T12	6		T317	12		-	-
auto[0]	values[0]	values[3]	22	1			T318	22		-	-		-	-
auto[0]	values[0]	values[4]	42	1			T245	24		T284	4		T201	14
auto[0]	values[0]	values[5]	62	1			T113	8		T278	10		T203	8
auto[0]	values[0]	values[6]	26	1			T186	6		T276	12		T319	8
auto[0]	values[0]	values[7]	16	1			T74	10		T320	6		-	-
auto[0]	values[1]	values[0]	70	1			T5	8		T8	12		T271	2
auto[0]	values[1]	values[1]	52	1			T26	6		T132	14		T266	8
auto[0]	values[1]	values[2]	24	1			T22	12		T244	12		-	-
auto[0]	values[1]	values[3]	18	1			T269	18		-	-		-	-
auto[0]	values[1]	values[4]	86	1			T107	18		T321	24		T322	26
auto[0]	values[1]	values[5]	20	1			T111	6		T105	14		-	-
auto[0]	values[1]	values[6]	62	1			T23	8		T180	28		T323	10
auto[0]	values[1]	values[7]	30	1			T285	8		T324	4		T106	14
auto[0]	values[2]	values[0]	60	1			T92	4		T47	30		T325	12
auto[0]	values[2]	values[2]	28	1			T104	14		T261	14		-	-
auto[0]	values[2]	values[3]	18	1			T196	4		T232	4		T326	10
auto[0]	values[2]	values[4]	66	1			T6	8		T253	26		T289	10
auto[0]	values[2]	values[5]	74	1			T9	8		T206	12		T130	10
auto[0]	values[2]	values[6]	26	1			T199	4		T293	22		-	-
auto[0]	values[2]	values[7]	44	1			T251	26		T272	18		-	-
auto[0]	values[3]	values[0]	18	1			T200	10		T327	8		-	-
auto[0]	values[3]	values[1]	20	1			T273	2		T268	10		T328	8
auto[0]	values[3]	values[2]	72	1			T237	16		T249	12		T329	16
auto[0]	values[3]	values[3]	32	1			T43	10		T46	2		T72	10
auto[0]	values[3]	values[4]	20	1			T239	20		-	-		-	-
auto[0]	values[3]	values[6]	22	1			T27	14		T252	8		-	-
auto[0]	values[3]	values[7]	4	1			T192	4		-	-		-	-
auto[0]	values[4]	values[0]	18	1			T25	6		T24	12		-	-
auto[0]	values[4]	values[1]	72	1			T44	12		T286	24		T295	36
auto[0]	values[4]	values[2]	82	1			T45	20		T238	20		T254	10
auto[0]	values[4]	values[4]	50	1			T79	28		T274	22		-	-
auto[0]	values[4]	values[6]	24	1			T277	2		T187	6		T270	6
auto[0]	values[4]	values[7]	64	1			T58	2		T83	34		T275	16
auto[0]	values[5]	values[0]	44	1			T221	12		T189	14		T257	16
auto[0]	values[5]	values[1]	14	1			T178	14		-	-		-	-
auto[0]	values[5]	values[2]	16	1			T188	6		T255	8		T260	2
auto[0]	values[5]	values[3]	30	1			T287	30		-	-		-	-
auto[0]	values[5]	values[4]	50	1			T330	20		T204	12		T216	10
auto[0]	values[5]	values[5]	46	1			T207	14		T331	10		T332	22
auto[0]	values[5]	values[6]	52	1			T333	24		T282	4		T334	20
auto[0]	values[6]	values[0]	30	1			T131	18		T335	2		T233	10
auto[0]	values[6]	values[1]	34	1			T82	20		T226	14		-	-
auto[0]	values[6]	values[2]	14	1			T202	8		T223	6		-	-
auto[0]	values[6]	values[4]	82	1			T197	4		T110	10		T265	8
auto[0]	values[6]	values[5]	52	1			T224	2		T267	4		T336	20
auto[0]	values[6]	values[6]	46	1			T108	8		T219	2		T337	8
auto[0]	values[6]	values[7]	32	1			T97	4		T208	26		T184	2
auto[0]	values[7]	values[0]	34	1			T93	22		T99	12		-	-
auto[0]	values[7]	values[1]	54	1			T210	10		T338	36		T339	8
auto[0]	values[7]	values[3]	24	1			T129	14		T262	6		T340	4
auto[0]	values[7]	values[4]	46	1			T209	18		T220	28		-	-
auto[0]	values[7]	values[5]	64	1			T28	4		T280	26		T283	4
auto[0]	values[7]	values[6]	58	1			T4	10		T81	28		T229	18
auto[0]	values[7]	values[7]	80	1			T205	30		T263	28		T112	22
auto[1]	values[0]	values[1]	24	1			T247	24		-	-		-	-
auto[1]	values[0]	values[3]	84	1			T288	28		T228	30		T90	26
auto[1]	values[0]	values[4]	18	1			T291	18		-	-		-	-
auto[1]	values[0]	values[7]	10	1			T211	10		-	-		-	-
auto[1]	values[1]	values[0]	46	1			T73	32		T259	14		-	-
auto[1]	values[1]	values[1]	12	1			T292	12		-	-		-	-
auto[1]	values[1]	values[2]	22	1			T234	4		T217	18		-	-
auto[1]	values[1]	values[6]	18	1			T91	18		-	-		-	-
auto[1]	values[1]	values[7]	28	1			T7	28		-	-		-	-
auto[1]	values[2]	values[0]	34	1			T71	34		-	-		-	-
auto[1]	values[2]	values[1]	14	1			T246	14		-	-		-	-
auto[1]	values[2]	values[2]	12	1			T341	12		-	-		-	-
auto[1]	values[2]	values[3]	24	1			T193	18		T342	6		-	-
auto[1]	values[3]	values[1]	62	1			T243	30		T343	32		-	-
auto[1]	values[3]	values[2]	4	1			T194	4		-	-		-	-
auto[1]	values[3]	values[4]	18	1			T86	18		-	-		-	-
auto[1]	values[3]	values[6]	40	1			T85	26		T344	14		-	-
auto[1]	values[3]	values[7]	34	1			T345	34		-	-		-	-
auto[1]	values[4]	values[2]	12	1			T346	12		-	-		-	-
auto[1]	values[4]	values[3]	22	1			T76	22		-	-		-	-
auto[1]	values[4]	values[4]	8	1			T218	8		-	-		-	-
auto[1]	values[4]	values[6]	2	1			T230	2		-	-		-	-
auto[1]	values[4]	values[7]	10	1			T100	10		-	-		-	-
auto[1]	values[5]	values[5]	10	1			T87	10		-	-		-	-
auto[1]	values[6]	values[0]	10	1			T347	10		-	-		-	-
auto[1]	values[6]	values[2]	24	1			T348	22		T241	2		-	-
auto[1]	values[6]	values[3]	2	1			T195	2		-	-		-	-
auto[1]	values[6]	values[4]	64	1			T250	24		T88	34		T349	6
auto[1]	values[6]	values[6]	26	1			T78	22		T350	4		-	-
auto[1]	values[6]	values[7]	26	1			T351	26		-	-		-	-
auto[1]	values[7]	values[1]	8	1			T89	8		-	-		-	-
auto[1]	values[7]	values[2]	30	1			T77	16		T215	14		-	-
auto[1]	values[7]	values[5]	20	1			T264	10		T352	10		-	-
auto[1]	values[7]	values[6]	28	1			T80	28		-	-		-	-
auto[1]	values[7]	values[7]	20	1			T84	16		T353	4		-	-