Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.26	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	2	58	96.67

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	2	58	96.67	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	108	1			T4	6		T5	2		T8	8
auto[ReadAddrCrossIntoMailbox]	46	1			T238	4		T242	10		T272	4
auto[ReadAddrCrossOutOfMailbox]	30	1			T202	4		T97	2		T237	4
auto[ReadAddrCrossAllMailbox]	44	1			T202	2		T238	4		T97	2
auto[ReadAddrOutsideMailbox]	844	1			T5	6		T7	6		T8	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

536

1

T4

3

T5

4

T7

3

auto[1]

536

1

T4

3

T5

4

T7

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	164	1			T7	4		T8	2		T79	4
read_ops[0x0b]	156	1			T8	2		T113	2		T82	2
read_ops[0x3b]	178	1			T4	4		T5	6		T8	2
read_ops[0x6b]	214	1			T4	2		T5	2		T7	2
read_ops[0xbb]	182	1			T8	4		T12	2		T110	4
read_ops[0xeb]	178	1			T197	2		T79	2		T76	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	2	58	96.67	2

Automatically Generated Cross Bins for cr_all

Element holes

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	NUMBER	STATUS
[read_ops[0x0b]]	[auto[ReadAddrCrossOutOfMailbox]]	*	--	--	2

Covered bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	7	1			T105	2		T271	1		T257	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	7	1			T105	2		T271	1		T257	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	1	1			T329	1		-	-		-	-
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	1	1			T329	1		-	-		-	-
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	2	1			T202	1		T356	1		-	-
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	2	1			T202	1		T356	1		-	-
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	2	1			T257	1		T330	1		-	-
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	2	1			T257	1		T330	1		-	-
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	70	1			T7	2		T8	1		T79	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	70	1			T7	2		T8	1		T79	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	13	1			T8	1		T202	1		T238	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	13	1			T8	1		T202	1		T238	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	5	1			T242	1		T322	1		T330	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	5	1			T242	1		T322	1		T330	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	4	1			T97	1		T322	1		T213	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	4	1			T97	1		T322	1		T213	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	56	1			T113	1		T82	1		T77	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	56	1			T113	1		T82	1		T77	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	5	1			T4	2		T8	1		T257	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	5	1			T4	2		T8	1		T257	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	7	1			T238	1		T322	2		T329	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	7	1			T238	1		T322	2		T329	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	1	1			T329	1		-	-		-	-
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	1	1			T329	1		-	-		-	-
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	3	1			T329	1		T330	2		-	-
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	3	1			T329	1		T330	2		-	-
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	73	1			T5	3		T9	1		T43	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	73	1			T5	3		T9	1		T43	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	9	1			T4	1		T5	1		T189	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	9	1			T4	1		T5	1		T189	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	4	1			T242	3		T322	1		-	-
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	4	1			T242	3		T322	1		-	-
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	2	1			T272	2		-	-		-	-
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	2	1			T272	2		-	-		-	-
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	8	1			T242	2		T249	2		T319	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	8	1			T242	2		T249	2		T319	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	84	1			T7	1		T107	3		T113	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	84	1			T7	1		T107	3		T113	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	13	1			T8	2		T105	2		T189	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	13	1			T8	2		T105	2		T189	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	2	1			T242	1		T272	1		-	-
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	2	1			T242	1		T272	1		-	-
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	4	1			T340	2		T330	1		T268	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	4	1			T340	2		T330	1		T268	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	3	1			T202	1		T238	1		T242	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	3	1			T202	1		T238	1		T242	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	69	1			T12	1		T110	2		T80	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	69	1			T12	1		T110	2		T80	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	7	1			T197	1		T238	1		T129	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	7	1			T197	1		T238	1		T129	3
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	4	1			T238	1		T272	1		T268	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	4	1			T238	1		T272	1		T268	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	6	1			T202	1		T97	1		T237	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	6	1			T202	1		T97	1		T237	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	2	1			T238	1		T332	1		-	-
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	2	1			T238	1		T332	1		-	-
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	70	1			T79	1		T76	1		T44	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	70	1			T79	1		T76	1		T44	1