Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
64.38	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	52	76	59.38

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	52	76	59.38	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	408	1			T5	8		T8	12		T28	4
values[1]	442	1			T76	22		T98	10		T104	14
values[2]	462	1			T9	8		T110	10		T79	28
values[3]	224	1			T7	28		T12	6		T192	4
values[4]	626	1			T43	10		T108	8		T193	18
values[5]	238	1			T4	10		T194	4		T195	2
values[6]	412	1			T75	2		T25	6		T26	6
values[7]	314	1			T107	18		T113	8		T196	4

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	502	1			T192	4		T76	22		T77	16
values[1]	366	1			T110	10		T46	2		T45	20
values[2]	374	1			T28	4		T79	28		T84	16
values[3]	220	1			T9	8		T107	18		T197	4
values[4]	400	1			T4	10		T7	28		T43	10
values[5]	472	1			T8	12		T75	2		T26	6
values[6]	380	1			T12	6		T194	4		T193	18
values[7]	412	1			T5	8		T25	6		T44	12

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3074

1

T4

10

T5

8

T7

28

auto[1]

52

1

T71

4

T73

10

T78

4

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	52	76	59.38	52

Automatically Generated Cross Bins for cr_all

Element holes

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[3]]	*	--	--	8
[auto[1]]	[values[6]]	*	--	--	8

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[3]]	[values[5]]	0	1	1
[auto[1]]	[values[0]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[0]]	[values[3] , values[4] , values[5] , values[6] , values[7]]	--	--	5
[auto[1]]	[values[1]]	[values[1] , values[2] , values[3]]	--	--	3
[auto[1]]	[values[1]]	[values[5] , values[6] , values[7]]	--	--	3
[auto[1]]	[values[2]]	[values[2]]	0	1	1
[auto[1]]	[values[2]]	[values[4] , values[5] , values[6] , values[7]]	--	--	4
[auto[1]]	[values[4] , values[5]]	[values[0] , values[1]]	--	--	4
[auto[1]]	[values[4] , values[5]]	[values[3]]	--	--	2
[auto[1]]	[values[4] , values[5]]	[values[5]]	--	--	2
[auto[1]]	[values[4] , values[5]]	[values[7]]	--	--	2
[auto[1]]	[values[7]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[7]]	[values[3] , values[4] , values[5] , values[6] , values[7]]	--	--	5

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	38	1			T77	16		T198	22		-	-
auto[0]	values[0]	values[1]	36	1			T46	2		T199	4		T200	10
auto[0]	values[0]	values[2]	56	1			T28	4		T201	14		T91	16
auto[0]	values[0]	values[3]	4	1			T197	4		-	-		-	-
auto[0]	values[0]	values[4]	56	1			T202	8		T203	8		T204	12
auto[0]	values[0]	values[5]	78	1			T8	12		T27	14		T205	30
auto[0]	values[0]	values[6]	48	1			T93	22		T206	12		T207	14
auto[0]	values[0]	values[7]	90	1			T5	8		T208	26		T180	28
auto[0]	values[1]	values[0]	136	1			T76	22		T98	10		T73	22
auto[0]	values[1]	values[1]	26	1			T6	8		T209	18		-	-
auto[0]	values[1]	values[2]	26	1			T210	10		T211	10		T212	6
auto[0]	values[1]	values[3]	6	1			T213	6		-	-		-	-
auto[0]	values[1]	values[4]	80	1			T71	30		T214	24		T124	22
auto[0]	values[1]	values[5]	94	1			T215	14		T191	28		T216	10
auto[0]	values[1]	values[6]	18	1			T217	18		-	-		-	-
auto[0]	values[1]	values[7]	42	1			T104	14		T99	12		T218	8
auto[0]	values[2]	values[0]	134	1			T219	2		T85	24		T220	28
auto[0]	values[2]	values[1]	76	1			T110	10		T92	4		T86	12
auto[0]	values[2]	values[2]	68	1			T79	28		T221	12		T222	8
auto[0]	values[2]	values[3]	36	1			T9	8		T223	6		T224	2
auto[0]	values[2]	values[4]	16	1			T225	2		T226	14		-	-
auto[0]	values[2]	values[5]	54	1			T82	20		T189	14		T227	14
auto[0]	values[2]	values[6]	50	1			T74	10		T58	2		T228	30
auto[0]	values[2]	values[7]	18	1			T229	18		-	-		-	-
auto[0]	values[3]	values[0]	14	1			T192	4		T230	2		T231	8
auto[0]	values[3]	values[1]	14	1			T232	4		T233	10		-	-
auto[0]	values[3]	values[2]	66	1			T178	14		T234	4		T235	2
auto[0]	values[3]	values[3]	16	1			T236	16		-	-		-	-
auto[0]	values[3]	values[4]	44	1			T7	28		T237	16		-	-
auto[0]	values[3]	values[6]	36	1			T12	6		T238	20		T130	10
auto[0]	values[3]	values[7]	34	1			T239	20		T240	12		T241	2
auto[0]	values[4]	values[0]	98	1			T242	24		T243	30		T244	12
auto[0]	values[4]	values[1]	94	1			T97	4		T47	30		T245	24
auto[0]	values[4]	values[2]	36	1			T246	14		T247	22		-	-
auto[0]	values[4]	values[3]	54	1			T105	14		T24	12		T248	4
auto[0]	values[4]	values[4]	82	1			T43	10		T81	28		T83	34
auto[0]	values[4]	values[5]	54	1			T108	8		T249	12		T250	24
auto[0]	values[4]	values[6]	92	1			T193	18		T251	26		T78	18
auto[0]	values[4]	values[7]	100	1			T252	8		T253	26		T254	10
auto[0]	values[5]	values[0]	20	1			T255	8		T256	12		-	-
auto[0]	values[5]	values[1]	18	1			T195	2		T257	16		-	-
auto[0]	values[5]	values[2]	40	1			T258	28		T259	12		-	-
auto[0]	values[5]	values[3]	2	1			T260	2		-	-		-	-
auto[0]	values[5]	values[4]	56	1			T4	10		T88	32		T261	14
auto[0]	values[5]	values[5]	52	1			T262	6		T263	28		T264	10
auto[0]	values[5]	values[6]	30	1			T194	4		T265	8		T266	8
auto[0]	values[5]	values[7]	14	1			T267	4		T268	10		-	-
auto[0]	values[6]	values[0]	30	1			T111	6		T269	18		T270	6
auto[0]	values[6]	values[1]	72	1			T45	20		T22	12		T271	2
auto[0]	values[6]	values[2]	36	1			T84	16		T272	18		T273	2
auto[0]	values[6]	values[3]	50	1			T274	22		T275	16		T276	12
auto[0]	values[6]	values[4]	38	1			T277	2		T131	18		T278	10
auto[0]	values[6]	values[5]	84	1			T75	2		T26	6		T132	14
auto[0]	values[6]	values[6]	40	1			T185	30		T279	10		-	-
auto[0]	values[6]	values[7]	62	1			T25	6		T44	12		T280	26
auto[0]	values[7]	values[0]	20	1			T196	4		T190	16		-	-
auto[0]	values[7]	values[1]	24	1			T100	10		T281	6		T282	4
auto[0]	values[7]	values[2]	36	1			T283	4		T188	6		T284	4
auto[0]	values[7]	values[3]	50	1			T107	18		T285	8		T129	14
auto[0]	values[7]	values[4]	14	1			T106	14		-	-		-	-
auto[0]	values[7]	values[5]	56	1			T113	8		T186	6		T286	24
auto[0]	values[7]	values[6]	58	1			T80	28		T287	30		-	-
auto[0]	values[7]	values[7]	52	1			T288	28		T289	10		T290	4
auto[1]	values[0]	values[2]	2	1			T91	2		-	-		-	-
auto[1]	values[1]	values[0]	10	1			T73	10		-	-		-	-
auto[1]	values[1]	values[4]	4	1			T71	4		-	-		-	-
auto[1]	values[2]	values[0]	2	1			T85	2		-	-		-	-
auto[1]	values[2]	values[1]	6	1			T86	6		-	-		-	-
auto[1]	values[2]	values[3]	2	1			T89	2		-	-		-	-
auto[1]	values[4]	values[2]	2	1			T247	2		-	-		-	-
auto[1]	values[4]	values[4]	8	1			T291	8		-	-		-	-
auto[1]	values[4]	values[6]	6	1			T78	4		T87	2		-	-
auto[1]	values[5]	values[2]	2	1			T259	2		-	-		-	-
auto[1]	values[5]	values[4]	2	1			T88	2		-	-		-	-
auto[1]	values[5]	values[6]	2	1			T292	2		-	-		-	-
auto[1]	values[7]	values[2]	4	1			T90	4		-	-		-	-