Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1326

1

T3

25

T14

3

T15

5

auto[1]

1298

1

T3

15

T14

8

T15

4

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

630

1

T15

9

T17

10

T62

11

auto[1]

1994

1

T3

40

T14

11

T17

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2383

1

T3

40

T14

11

T15

5

auto[1]

241

1

T15

4

T17

5

T62

5

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	566	1			T3	9		T14	2		T17	4
valid[1]	550	1			T3	8		T14	4		T15	6
valid[2]	510	1			T3	12		T14	2		T17	4
valid[3]	485	1			T3	3		T14	2		T15	1
valid[4]	513	1			T3	8		T14	1		T15	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	41	1			T17	3		T62	2		T66	3
auto[0]	auto[0]	valid[0]	auto[1]	232	1			T3	5		T14	1		T62	1
auto[0]	auto[0]	valid[1]	auto[0]	37	1			T15	2		T17	1		T62	1
auto[0]	auto[0]	valid[1]	auto[1]	206	1			T3	6		T20	1		T119	1
auto[0]	auto[0]	valid[2]	auto[0]	42	1			T65	1		T109	2		T386	1
auto[0]	auto[0]	valid[2]	auto[1]	192	1			T3	8		T14	1		T17	1
auto[0]	auto[0]	valid[3]	auto[0]	39	1			T65	2		T66	1		T69	1
auto[0]	auto[0]	valid[3]	auto[1]	169	1			T3	1		T14	1		T119	1
auto[0]	auto[0]	valid[4]	auto[0]	44	1			T15	1		T62	1		T66	2
auto[0]	auto[0]	valid[4]	auto[1]	192	1			T3	5		T20	1		T66	1
auto[0]	auto[1]	valid[0]	auto[0]	37	1			T65	1		T66	2		T109	1
auto[0]	auto[1]	valid[0]	auto[1]	213	1			T3	4		T14	1		T119	1
auto[0]	auto[1]	valid[1]	auto[0]	42	1			T15	2		T62	1		T109	4
auto[0]	auto[1]	valid[1]	auto[1]	217	1			T3	2		T14	4		T62	1
auto[0]	auto[1]	valid[2]	auto[0]	41	1			T17	1		T66	2		T109	1
auto[0]	auto[1]	valid[2]	auto[1]	185	1			T3	4		T14	1		T20	1
auto[0]	auto[1]	valid[3]	auto[0]	26	1			T62	1		T65	1		T386	1
auto[0]	auto[1]	valid[3]	auto[1]	198	1			T3	2		T14	1		T121	1
auto[0]	auto[1]	valid[4]	auto[0]	40	1			T65	1		T66	1		T109	1
auto[0]	auto[1]	valid[4]	auto[1]	190	1			T3	3		T14	1		T119	2
auto[1]	auto[0]	valid[0]	auto[0]	29	1			T17	1		T62	1		T66	2
auto[1]	auto[0]	valid[1]	auto[0]	23	1			T109	2		T386	1		T412	1
auto[1]	auto[0]	valid[2]	auto[0]	31	1			T17	2		T394	1		T412	1
auto[1]	auto[0]	valid[3]	auto[0]	25	1			T15	1		T65	3		T66	3
auto[1]	auto[0]	valid[4]	auto[0]	24	1			T15	1		T17	2		T65	1
auto[1]	auto[1]	valid[0]	auto[0]	14	1			T54	1		T419	4		T405	1
auto[1]	auto[1]	valid[1]	auto[0]	25	1			T15	2		T62	1		T66	1
auto[1]	auto[1]	valid[2]	auto[0]	19	1			T66	1		T109	3		T394	1
auto[1]	auto[1]	valid[3]	auto[0]	28	1			T62	3		T109	2		T68	2
auto[1]	auto[1]	valid[4]	auto[0]	23	1			T65	2		T386	2		T387	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal