Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16942

1

T13

2

T15

190

T17

186

auto[1]

19556

1

T3

696

T14

11

T17

29

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30074

1

T3

696

T13

1

T14

11

auto[1]

6424

1

T13

1

T15

64

T17

67

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	19051	1			T3	386		T13	1		T14	11
others[1]	3048	1			T3	49		T15	18		T17	18
others[2]	3037	1			T3	56		T15	16		T17	20
others[3]	3376	1			T3	54		T13	1		T15	12
interest[1]	1978	1			T3	41		T15	7		T17	12
interest[4]	12510	1			T3	246		T14	11		T15	64
interest[64]	6008	1			T3	110		T15	37		T17	36

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	5358	1			T13	1		T15	69		T17	62
auto[0]	auto[0]	others[1]	915	1			T15	11		T17	6		T21	1
auto[0]	auto[0]	others[2]	889	1			T15	12		T17	12		T62	23
auto[0]	auto[0]	others[3]	975	1			T15	5		T17	11		T62	24
auto[0]	auto[0]	interest[1]	573	1			T15	6		T17	5		T62	18
auto[0]	auto[0]	interest[4]	3437	1			T15	42		T17	41		T21	5
auto[0]	auto[0]	interest[64]	1808	1			T15	23		T17	23		T62	54
auto[0]	auto[1]	others[0]	10343	1			T3	386		T14	11		T17	16
auto[0]	auto[1]	others[1]	1597	1			T3	49		T17	4		T62	6
auto[0]	auto[1]	others[2]	1613	1			T3	56		T17	2		T62	5
auto[0]	auto[1]	others[3]	1795	1			T3	54		T17	2		T62	8
auto[0]	auto[1]	interest[1]	1057	1			T3	41		T17	1		T62	6
auto[0]	auto[1]	interest[4]	6865	1			T3	246		T14	11		T17	12
auto[0]	auto[1]	interest[64]	3151	1			T3	110		T17	4		T62	11
auto[1]	auto[0]	others[0]	3350	1			T15	31		T17	33		T21	6
auto[1]	auto[0]	others[1]	536	1			T15	7		T17	8		T62	13
auto[1]	auto[0]	others[2]	535	1			T15	4		T17	6		T62	11
auto[1]	auto[0]	others[3]	606	1			T13	1		T15	7		T17	5
auto[1]	auto[0]	interest[1]	348	1			T15	1		T17	6		T21	1
auto[1]	auto[0]	interest[4]	2208	1			T15	22		T17	25		T21	3
auto[1]	auto[0]	interest[64]	1049	1			T15	14		T17	9		T62	24

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal