Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	450	1			T32	14		T33	7		T34	11
all_values[1]	450	1			T32	14		T33	7		T34	11
all_values[2]	450	1			T32	14		T33	7		T34	11
all_values[3]	450	1			T32	14		T33	7		T34	11
all_values[4]	450	1			T32	14		T33	7		T34	11
all_values[5]	450	1			T32	14		T33	7		T34	11
all_values[6]	450	1			T32	14		T33	7		T34	11
all_values[7]	450	1			T32	14		T33	7		T34	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1987

1

T32

58

T33

42

T34

45

auto[1]

1613

1

T32

54

T33

14

T34

43

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1494

1

T32

51

T33

25

T34

29

auto[1]

2106

1

T32

61

T33

31

T34

59

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2104

1

T32

70

T33

37

T34

44

auto[1]

1496

1

T32

42

T33

19

T34

44

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	83	1			T32	2		T33	1		T34	3
all_values[0]	auto[0]	auto[0]	auto[1]	61	1			T32	4		T33	3		T34	1
all_values[0]	auto[0]	auto[1]	auto[0]	56	1			T32	2		T41	1		T354	1
all_values[0]	auto[0]	auto[1]	auto[1]	40	1			T33	1		T174	1		T355	4
all_values[0]	auto[1]	auto[0]	auto[1]	113	1			T32	2		T33	2		T34	5
all_values[0]	auto[1]	auto[1]	auto[1]	97	1			T32	4		T34	2		T41	5
all_values[1]	auto[0]	auto[0]	auto[0]	96	1			T32	3		T174	2		T355	7
all_values[1]	auto[0]	auto[0]	auto[1]	55	1			T33	2		T34	1		T41	3
all_values[1]	auto[0]	auto[1]	auto[0]	67	1			T32	2		T34	1		T41	3
all_values[1]	auto[0]	auto[1]	auto[1]	46	1			T32	2		T34	4		T41	1
all_values[1]	auto[1]	auto[0]	auto[1]	98	1			T32	3		T33	5		T34	1
all_values[1]	auto[1]	auto[1]	auto[1]	88	1			T32	4		T34	4		T41	3
all_values[2]	auto[0]	auto[0]	auto[0]	108	1			T32	1		T33	3		T34	2
all_values[2]	auto[0]	auto[0]	auto[1]	33	1			T32	1		T41	1		T355	2
all_values[2]	auto[0]	auto[1]	auto[0]	99	1			T32	6		T34	1		T41	3
all_values[2]	auto[0]	auto[1]	auto[1]	36	1			T32	2		T33	1		T34	1
all_values[2]	auto[1]	auto[0]	auto[1]	100	1			T32	3		T33	3		T34	6
all_values[2]	auto[1]	auto[1]	auto[1]	74	1			T32	1		T34	1		T41	3
all_values[3]	auto[0]	auto[0]	auto[0]	88	1			T32	2		T33	4		T34	6
all_values[3]	auto[0]	auto[0]	auto[1]	48	1			T33	1		T354	1		T355	2
all_values[3]	auto[0]	auto[1]	auto[0]	68	1			T32	2		T34	1		T41	2
all_values[3]	auto[0]	auto[1]	auto[1]	46	1			T32	3		T41	1		T174	1
all_values[3]	auto[1]	auto[0]	auto[1]	112	1			T32	3		T33	2		T34	2
all_values[3]	auto[1]	auto[1]	auto[1]	88	1			T32	4		T34	2		T41	2
all_values[4]	auto[0]	auto[0]	auto[0]	128	1			T32	1		T33	5		T34	1
all_values[4]	auto[0]	auto[0]	auto[1]	36	1			T32	2		T33	1		T34	1
all_values[4]	auto[0]	auto[1]	auto[0]	65	1			T32	2		T34	2		T41	3
all_values[4]	auto[0]	auto[1]	auto[1]	41	1			T32	1		T34	1		T41	2
all_values[4]	auto[1]	auto[0]	auto[1]	95	1			T32	6		T33	1		T41	2
all_values[4]	auto[1]	auto[1]	auto[1]	85	1			T32	2		T34	6		T41	2
all_values[5]	auto[0]	auto[0]	auto[0]	143	1			T32	4		T33	1		T34	3
all_values[5]	auto[0]	auto[1]	auto[0]	124	1			T32	7		T33	3		T34	2
all_values[5]	auto[1]	auto[0]	auto[1]	99	1			T32	1		T33	1		T34	3
all_values[5]	auto[1]	auto[1]	auto[1]	84	1			T32	2		T33	2		T34	3
all_values[6]	auto[0]	auto[0]	auto[0]	104	1			T32	8		T33	2		T41	3
all_values[6]	auto[0]	auto[0]	auto[1]	50	1			T32	2		T33	1		T34	2
all_values[6]	auto[0]	auto[1]	auto[0]	80	1			T32	1		T33	1		T34	1
all_values[6]	auto[0]	auto[1]	auto[1]	31	1			T33	1		T34	1		T174	2
all_values[6]	auto[1]	auto[0]	auto[1]	105	1			T32	3		T33	1		T34	3
all_values[6]	auto[1]	auto[1]	auto[1]	80	1			T33	1		T34	4		T41	1
all_values[7]	auto[0]	auto[0]	auto[0]	108	1			T32	4		T33	2		T34	2
all_values[7]	auto[0]	auto[0]	auto[1]	30	1			T32	1		T34	1		T41	1
all_values[7]	auto[0]	auto[1]	auto[0]	77	1			T32	4		T33	3		T34	4
all_values[7]	auto[0]	auto[1]	auto[1]	57	1			T32	1		T33	1		T34	2
all_values[7]	auto[1]	auto[0]	auto[1]	94	1			T32	2		T33	1		T34	2
all_values[7]	auto[1]	auto[1]	auto[1]	84	1			T32	2		T41	2		T174	7

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal