Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	253399	1			T1	1		T3	1		T7	304
all_values[1]	253399	1			T1	1		T3	1		T7	304
all_values[2]	253399	1			T1	1		T3	1		T7	304
all_values[3]	253399	1			T1	1		T3	1		T7	304
all_values[4]	253399	1			T1	1		T3	1		T7	304
all_values[5]	253399	1			T1	1		T3	1		T7	304
all_values[6]	253399	1			T1	1		T3	1		T7	304
all_values[7]	253399	1			T1	1		T3	1		T7	304

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2024882

1

T1

8

T3

8

T7

2432

auto[1]

2310

1

T32

79

T33

80

T41

108

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2025127

1

T1

8

T3

8

T7

2427

auto[1]

2065

1

T7

5

T16

1

T62

1

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	253016	1			T1	1		T3	1		T7	304
all_values[0]	auto[0]	auto[1]	113	1			T32	1		T33	4		T41	4
all_values[0]	auto[1]	auto[0]	174	1			T32	9		T33	2		T41	11
all_values[0]	auto[1]	auto[1]	96	1			T32	2		T33	3		T41	3
all_values[1]	auto[0]	auto[0]	252988	1			T1	1		T3	1		T7	304
all_values[1]	auto[0]	auto[1]	110	1			T32	1		T33	1		T41	5
all_values[1]	auto[1]	auto[0]	176	1			T32	8		T33	4		T41	9
all_values[1]	auto[1]	auto[1]	125	1			T32	2		T33	4		T41	8
all_values[2]	auto[0]	auto[0]	253018	1			T1	1		T3	1		T7	304
all_values[2]	auto[0]	auto[1]	122	1			T32	5		T33	6		T41	6
all_values[2]	auto[1]	auto[0]	173	1			T32	12		T33	7		T41	5
all_values[2]	auto[1]	auto[1]	86	1			T32	3		T33	1		T41	5
all_values[3]	auto[0]	auto[0]	252965	1			T1	1		T3	1		T7	304
all_values[3]	auto[0]	auto[1]	135	1			T32	3		T33	3		T41	8
all_values[3]	auto[1]	auto[0]	174	1			T32	5		T33	10		T41	7
all_values[3]	auto[1]	auto[1]	125	1			T32	4		T33	2		T41	4
all_values[4]	auto[0]	auto[0]	252955	1			T1	1		T3	1		T7	304
all_values[4]	auto[0]	auto[1]	134	1			T32	4		T33	2		T132	3
all_values[4]	auto[1]	auto[0]	180	1			T32	7		T33	6		T41	12
all_values[4]	auto[1]	auto[1]	130	1			T32	4		T33	6		T41	5
all_values[5]	auto[0]	auto[0]	252781	1			T1	1		T3	1		T7	299
all_values[5]	auto[0]	auto[1]	305	1			T7	5		T16	1		T62	1
all_values[5]	auto[1]	auto[0]	185	1			T32	7		T33	6		T41	5
all_values[5]	auto[1]	auto[1]	128	1			T32	5		T33	4		T41	6
all_values[6]	auto[0]	auto[0]	252987	1			T1	1		T3	1		T7	304
all_values[6]	auto[0]	auto[1]	133	1			T32	9		T33	2		T41	8
all_values[6]	auto[1]	auto[0]	183	1			T32	5		T33	12		T41	7
all_values[6]	auto[1]	auto[1]	96	1			T33	4		T41	3		T177	2
all_values[7]	auto[0]	auto[0]	253011	1			T1	1		T3	1		T7	304
all_values[7]	auto[0]	auto[1]	109	1			T32	4		T33	4		T41	3
all_values[7]	auto[1]	auto[0]	161	1			T32	3		T33	8		T41	12
all_values[7]	auto[1]	auto[1]	118	1			T32	3		T33	1		T41	6