Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
71.31	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	1	37	97.37
Crosses	84	34	50	59.52

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	1	1	50.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	29	19	39.58	100	1	1	0
cr_modeXdummyXnum_lanes	36	5	31	86.11	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	1002	1			T6	2		T11	6		T43	4
auto[SpiFlashAddrCfg]	866	1			T5	4		T6	2		T8	2
auto[SpiFlashAddr3b]	1006	1			T4	2		T5	4		T9	2
auto[SpiFlashAddr4b]	930	1			T4	4		T5	7		T8	4

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2986

1

T4

6

T5

15

T8

6

auto[1]

818

1

T6

4

T11

22

T71

24

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1935

1

T4

6

T5

11

T6

2

auto[1]

1869

1

T5

4

T6

2

T9

8

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1410	1			T6	4		T11	10		T43	4
values[1]	85	1			T5	3		T12	7		T274	2
values[2]	151	1			T43	4		T45	4		T27	4
values[3]	234	1			T76	8		T75	4		T45	4
values[4]	182	1			T11	2		T76	2		T98	2
values[5]	159	1			T5	4		T76	2		T45	4
values[6]	235	1			T9	4		T11	2		T12	4
values[7]	169	1			T9	2		T11	4		T12	5
values[8]	1179	1			T4	6		T5	8		T8	6

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3292

1

T4

6

T6

4

T8

6

auto[1]

512

1

T5

15

T12

23

T95

3

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

3688

1

T4

6

T5

15

T6

4

write

116

1

T45

4

T69

2

T70

6

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

1819

1

T4

4

T5

8

T6

2

valids[0x1]

1985

1

T4

2

T5

7

T6

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	188	1			T49	4		T45	2		T27	2
internal_process_ops[0x5a]	164	1			T4	2		T45	4		T105	2
internal_process_ops[0x05]	170	1			T6	2		T43	4		T76	2
internal_process_ops[0x35]	204	1			T11	4		T99	2		T74	4
internal_process_ops[0x15]	170	1			T44	2		T130	2		T131	4
internal_process_ops[0x03]	260	1			T5	4		T11	2		T75	4
internal_process_ops[0x0b]	274	1			T5	3		T12	7		T76	8
internal_process_ops[0x3b]	335	1			T9	2		T12	5		T43	4
internal_process_ops[0x6b]	183	1			T11	2		T12	4		T75	4
internal_process_ops[0xbb]	290	1			T5	4		T9	2		T11	2
internal_process_ops[0xeb]	288	1			T4	4		T5	4		T11	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3756

1

T4

6

T5

15

T6

4

auto[1]

48

1

T70

6

T72

2

T73

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_upload

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3804

1

T4

6

T5

15

T6

4

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	29	19	39.58	29
Automatically Generated Cross Bins	48	29	19	39.58	29
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Element holes

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[write]	*	[auto[0]]	[auto[1]]	--	--	4
[auto[0]]	[write]	*	[auto[1]]	[auto[0]]	--	--	4
[auto[1]]	[read]	[auto[SpiFlashAddrDisabled]]	*	[auto[0]]	--	--	2
[auto[1]]	[write]	*	*	*	--	--	16

Uncovered bins

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[read]	[auto[SpiFlashAddrCfg] , auto[SpiFlashAddr3b] , auto[SpiFlashAddr4b]]	[auto[1]]	[auto[0]]	--	--	3

Covered bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

806

1

T43

4

T76

4

T44

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

180

1

T6

2

T11

6

T71

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

498

1

T8

2

T9

2

T43

10

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

172

1

T6

2

T11

6

T71

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

584

1

T4

2

T9

2

T43

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

224

1

T11

2

T71

14

T104

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

518

1

T4

4

T8

4

T9

8

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

194

1

T11

8

T71

4

T194

16

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

12

1

T210

2

T222

2

T249

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

4

1

T299

4

-

-

-

-

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

20

1

T69

2

T200

2

T300

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

6

1

T79

2

T82

2

T298

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

10

1

T92

4

T301

2

T302

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

30

1

T70

6

T72

2

T77

8

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

26

1

T45

4

T203

2

T222

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

8

1

T73

2

T80

2

T83

2

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

170

1

T5

4

T95

3

T96

5

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

158

1

T5

4

T12

16

T132

4

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

184

1

T5

7

T12

7

T96

5

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	5	31	86.11	5

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Uncovered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[1]]	[valids[0x0]]	0	1	1
[auto[1]]	[values[1]]	[valids[0x0]]	0	1	1
[auto[1]]	[values[2] , values[3] , values[4]]	[valids[0x1]]	--	--	3

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	254	1			T6	2		T11	6		T75	2
auto[0]	values[0]	valids[0x1]	1110	1			T6	2		T11	4		T43	4
auto[0]	values[1]	valids[0x1]	66	1			T274	2		T240	4		T244	2
auto[0]	values[2]	valids[0x0]	76	1			T43	4		T27	4		T274	8
auto[0]	values[2]	valids[0x1]	52	1			T45	4		T105	2		T274	4
auto[0]	values[3]	valids[0x0]	122	1			T196	2		T71	2		T46	14
auto[0]	values[3]	valids[0x1]	74	1			T76	8		T75	4		T45	4
auto[0]	values[4]	valids[0x0]	88	1			T11	2		T76	2		T71	10
auto[0]	values[4]	valids[0x1]	66	1			T98	2		T194	4		T102	2
auto[0]	values[5]	valids[0x0]	62	1			T76	2		T45	4		T74	2
auto[0]	values[5]	valids[0x1]	38	1			T71	2		T195	6		T300	2
auto[0]	values[6]	valids[0x0]	136	1			T9	4		T99	2		T225	2
auto[0]	values[6]	valids[0x1]	56	1			T11	2		T76	2		T49	2
auto[0]	values[7]	valids[0x0]	108	1			T9	2		T11	2		T74	2
auto[0]	values[7]	valids[0x1]	44	1			T11	2		T44	2		T27	4
auto[0]	values[8]	valids[0x0]	606	1			T4	4		T8	6		T9	6
auto[0]	values[8]	valids[0x1]	334	1			T4	2		T76	2		T75	4
auto[1]	values[0]	valids[0x0]	2	1			T303	2		-	-		-	-
auto[1]	values[0]	valids[0x1]	44	1			T96	5		T304	3		T305	3
auto[1]	values[1]	valids[0x1]	19	1			T5	3		T12	7		T306	1
auto[1]	values[2]	valids[0x0]	23	1			T305	11		T307	4		T308	4
auto[1]	values[3]	valids[0x0]	38	1			T95	2		T309	4		T310	8
auto[1]	values[4]	valids[0x0]	28	1			T311	9		T310	4		T312	11
auto[1]	values[5]	valids[0x0]	48	1			T5	4		T97	4		T313	4
auto[1]	values[5]	valids[0x1]	11	1			T311	3		T314	6		T315	2
auto[1]	values[6]	valids[0x0]	30	1			T12	4		T97	7		T316	3
auto[1]	values[6]	valids[0x1]	13	1			T132	4		T313	4		T316	5
auto[1]	values[7]	valids[0x0]	9	1			T12	5		T317	4		-	-
auto[1]	values[7]	valids[0x1]	8	1			T309	2		T318	6		-	-
auto[1]	values[8]	valids[0x0]	189	1			T5	4		T12	7		T96	5
auto[1]	values[8]	valids[0x1]	50	1			T5	4		T95	1		T97	2