Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
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Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
36.36 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv


Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 16 2 14 87.50
Crosses 72 54 18 25.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_busy_bit 2 1 1 50.00 100 1 1 2
cp_is_host_read 2 0 2 100.00 100 1 1 2
cp_other_status 8 0 8 100.00 100 1 1 8
cp_sw_read_while_csb_active 2 0 2 100.00 100 1 1 2
cp_wel_bit 2 1 1 50.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all_except_csb 64 48 16 25.00 100 1 1 0
cr_busyXwelXcsb 8 6 2 25.00 100 1 1 0


Summary for Variable cp_busy_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_busy_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1699271 1 T4 8963 T5 3619 T6 1


Summary for Variable cp_is_host_read

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_is_host_read

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1543589 1 T4 8963 T5 3619 T6 1
auto[1] 155682 1 T43 5730 T44 2 T45 512


Summary for Variable cp_other_status

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 8 0 8 100.00


Automatically Generated Bins for cp_other_status

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:524287] 346516 1 T4 402 T5 875 T6 1
auto[524288:1048575] 218789 1 T4 2 T5 29 T12 214
auto[1048576:1572863] 183750 1 T5 208 T12 327 T44 59
auto[1572864:2097151] 191375 1 T4 4 T5 6 T12 3
auto[2097152:2621439] 232103 1 T4 1 T5 1242 T12 7
auto[2621440:3145727] 170296 1 T4 3013 T5 83 T12 342
auto[3145728:3670015] 149033 1 T4 677 T5 486 T49 1
auto[3670016:4194303] 207409 1 T4 4864 T5 690 T12 32


Summary for Variable cp_sw_read_while_csb_active

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sw_read_while_csb_active

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 165441 1 T4 27 T5 36 T6 1
auto[1] 1533830 1 T4 8936 T5 3583 T12 1348


Summary for Variable cp_wel_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_wel_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1699271 1 T4 8963 T5 3619 T6 1


Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 48 16 25.00 48


Automatically Generated Cross Bins for cr_all_except_csb

Element holes
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * * -- -- 16
[auto[1]] * * * -- -- 32


Covered bins
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0:524287] auto[0] 258957 1 T4 402 T5 875 T6 1
auto[0] auto[0] auto[0:524287] auto[1] 87559 1 T43 5730 T44 2 T45 512
auto[0] auto[0] auto[524288:1048575] auto[0] 210160 1 T4 2 T5 29 T12 214
auto[0] auto[0] auto[524288:1048575] auto[1] 8629 1 T131 505 T192 512 T118 1
auto[0] auto[0] auto[1048576:1572863] auto[0] 166058 1 T5 208 T12 327 T44 59
auto[0] auto[0] auto[1048576:1572863] auto[1] 17692 1 T117 1 T135 3233 T193 779
auto[0] auto[0] auto[1572864:2097151] auto[0] 178206 1 T4 4 T5 6 T12 3
auto[0] auto[0] auto[1572864:2097151] auto[1] 13169 1 T130 1011 T117 5 T135 2981
auto[0] auto[0] auto[2097152:2621439] auto[0] 224272 1 T4 1 T5 1242 T12 7
auto[0] auto[0] auto[2097152:2621439] auto[1] 7831 1 T131 1 T135 514 T193 762
auto[0] auto[0] auto[2621440:3145727] auto[0] 164027 1 T4 3013 T5 83 T12 342
auto[0] auto[0] auto[2621440:3145727] auto[1] 6269 1 T135 1563 T193 140 T192 2
auto[0] auto[0] auto[3145728:3670015] auto[0] 140280 1 T4 677 T5 486 T49 1
auto[0] auto[0] auto[3145728:3670015] auto[1] 8753 1 T135 2134 T193 518 T48 1094
auto[0] auto[0] auto[3670016:4194303] auto[0] 201629 1 T4 4864 T5 690 T12 32
auto[0] auto[0] auto[3670016:4194303] auto[1] 5780 1 T130 525 T131 1849 T117 5


Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 6 2 25.00 6


Automatically Generated Cross Bins for cr_busyXwelXcsb

Element holes
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * -- -- 2
[auto[1]] * * -- -- 4


Covered bins
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 165441 1 T4 27 T5 36 T6 1
auto[0] auto[0] auto[1] 1533830 1 T4 8936 T5 3583 T12 1348

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