Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
79.45	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	30	98	76.56

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	30	98	76.56	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2474

1

T4

6

T8

6

T9

12

auto[1]

818

1

T6

4

T11

22

T71

24

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	440	1			T4	6		T6	4		T11	22
values[1]	344	1			T74	16		T71	24		T102	2
values[2]	476	1			T76	24		T27	22		T196	6
values[3]	470	1			T99	8		T105	2		T46	24
values[4]	332	1			T8	6		T45	32		T28	8
values[5]	418	1			T98	6		T194	34		T197	4
values[6]	358	1			T49	10		T44	10		T75	20
values[7]	454	1			T9	12		T130	6		T131	4

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	416	1			T44	10		T45	32		T105	2
values[1]	408	1			T99	8		T74	16		T27	22
values[2]	478	1			T76	24		T196	6		T71	24
values[3]	358	1			T4	6		T8	6		T98	6
values[4]	432	1			T9	12		T75	20		T29	12
values[5]	402	1			T11	22		T43	24		T46	24
values[6]	332	1			T131	4		T91	6		T24	20
values[7]	466	1			T6	4		T49	10		T130	6

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	30	98	76.56	30

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[2]]	[values[4]]	0	1	1
[auto[0]]	[values[4]]	[values[2]]	0	1	1
[auto[1]]	[values[0]]	[values[1]]	0	1	1
[auto[1]]	[values[0]]	[values[3] , values[4]]	--	--	2
[auto[1]]	[values[0]]	[values[6]]	0	1	1
[auto[1]]	[values[1]]	[values[4]]	0	1	1
[auto[1]]	[values[1]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[2]]	[values[1]]	0	1	1
[auto[1]]	[values[2]]	[values[3]]	0	1	1
[auto[1]]	[values[2]]	[values[6]]	0	1	1
[auto[1]]	[values[3]]	[values[6]]	0	1	1
[auto[1]]	[values[4]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[4]]	[values[3] , values[4] , values[5]]	--	--	3
[auto[1]]	[values[4]]	[values[7]]	0	1	1
[auto[1]]	[values[5]]	[values[1] , values[2] , values[3] , values[4]]	--	--	4
[auto[1]]	[values[6]]	[values[1]]	0	1	1
[auto[1]]	[values[6]]	[values[5] , values[6]]	--	--	2
[auto[1]]	[values[7]]	[values[1]]	0	1	1
[auto[1]]	[values[7]]	[values[3]]	0	1	1
[auto[1]]	[values[7]]	[values[5]]	0	1	1
[auto[1]]	[values[7]]	[values[7]]	0	1	1

Covered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	28	1			T117	6		T257	22		-	-
auto[0]	values[0]	values[1]	24	1			T263	24		-	-		-	-
auto[0]	values[0]	values[2]	22	1			T219	2		T284	6		T319	14
auto[0]	values[0]	values[3]	40	1			T4	6		T106	18		T229	6
auto[0]	values[0]	values[4]	78	1			T236	32		T250	8		T320	24
auto[0]	values[0]	values[5]	44	1			T43	24		T193	14		T211	6
auto[0]	values[0]	values[6]	70	1			T278	8		T234	26		T321	22
auto[0]	values[0]	values[7]	46	1			T69	4		T243	12		T183	16
auto[0]	values[1]	values[0]	38	1			T241	8		T206	18		T239	12
auto[0]	values[1]	values[1]	26	1			T74	16		T281	10		-	-
auto[0]	values[1]	values[2]	60	1			T199	10		T322	18		T216	2
auto[0]	values[1]	values[3]	30	1			T252	4		T205	10		T222	16
auto[0]	values[1]	values[4]	12	1			T323	12		-	-		-	-
auto[0]	values[1]	values[5]	14	1			T324	14		-	-		-	-
auto[0]	values[1]	values[6]	34	1			T48	8		T247	16		T218	10
auto[0]	values[1]	values[7]	2	1			T102	2		-	-		-	-
auto[0]	values[2]	values[0]	10	1			T325	10		-	-		-	-
auto[0]	values[2]	values[1]	98	1			T27	22		T269	8		T287	12
auto[0]	values[2]	values[2]	56	1			T76	24		T196	6		T244	6
auto[0]	values[2]	values[3]	56	1			T288	18		T326	26		T327	2
auto[0]	values[2]	values[5]	2	1			T200	2		-	-		-	-
auto[0]	values[2]	values[6]	6	1			T101	6		-	-		-	-
auto[0]	values[2]	values[7]	58	1			T192	26		T328	14		T282	14
auto[0]	values[3]	values[0]	22	1			T105	2		T286	2		T329	8
auto[0]	values[3]	values[1]	16	1			T99	8		T330	8		-	-
auto[0]	values[3]	values[2]	64	1			T195	30		T123	2		T331	4
auto[0]	values[3]	values[3]	68	1			T272	18		T57	4		T203	18
auto[0]	values[3]	values[4]	112	1			T29	12		T220	22		T268	34
auto[0]	values[3]	values[5]	24	1			T46	24		-	-		-	-
auto[0]	values[3]	values[6]	46	1			T24	20		T107	10		T204	14
auto[0]	values[3]	values[7]	20	1			T86	12		T228	8		-	-
auto[0]	values[4]	values[0]	32	1			T45	32		-	-		-	-
auto[0]	values[4]	values[1]	70	1			T293	20		T212	20		T332	12
auto[0]	values[4]	values[3]	34	1			T8	6		T333	12		T283	16
auto[0]	values[4]	values[4]	20	1			T242	2		T334	18		-	-
auto[0]	values[4]	values[5]	20	1			T256	20		-	-		-	-
auto[0]	values[4]	values[6]	40	1			T238	14		T335	26		-	-
auto[0]	values[4]	values[7]	90	1			T28	8		T336	14		T258	18
auto[0]	values[5]	values[0]	28	1			T221	2		T265	26		-	-
auto[0]	values[5]	values[1]	100	1			T47	14		T135	14		T92	10
auto[0]	values[5]	values[2]	28	1			T337	10		T188	2		T338	16
auto[0]	values[5]	values[3]	22	1			T98	6		T26	16		-	-
auto[0]	values[5]	values[4]	42	1			T134	12		T246	6		T339	14
auto[0]	values[5]	values[5]	56	1			T197	4		T103	26		T249	26
auto[0]	values[5]	values[6]	2	1			T271	2		-	-		-	-
auto[0]	values[5]	values[7]	36	1			T210	28		T209	8		-	-
auto[0]	values[6]	values[0]	36	1			T44	10		T118	16		T290	10
auto[0]	values[6]	values[1]	28	1			T340	28		-	-		-	-
auto[0]	values[6]	values[2]	18	1			T240	18		-	-		-	-
auto[0]	values[6]	values[3]	44	1			T208	22		T255	12		T341	10
auto[0]	values[6]	values[4]	46	1			T75	20		T231	10		T235	10
auto[0]	values[6]	values[5]	48	1			T25	8		T294	12		T232	12
auto[0]	values[6]	values[6]	40	1			T266	14		T342	6		T233	20
auto[0]	values[6]	values[7]	22	1			T49	10		T89	2		T227	10
auto[0]	values[7]	values[0]	34	1			T292	12		T343	22		-	-
auto[0]	values[7]	values[1]	22	1			T270	22		-	-		-	-
auto[0]	values[7]	values[2]	80	1			T136	8		T300	34		T344	26
auto[0]	values[7]	values[3]	30	1			T345	8		T346	22		-	-
auto[0]	values[7]	values[4]	30	1			T9	12		T347	2		T214	16
auto[0]	values[7]	values[5]	62	1			T225	12		T184	12		T348	24
auto[0]	values[7]	values[6]	38	1			T131	4		T108	18		T226	4
auto[0]	values[7]	values[7]	50	1			T130	6		T274	30		T295	14
auto[1]	values[0]	values[0]	26	1			T73	26		-	-		-	-
auto[1]	values[0]	values[2]	14	1			T207	14		-	-		-	-
auto[1]	values[0]	values[5]	22	1			T11	22		-	-		-	-
auto[1]	values[0]	values[7]	26	1			T6	4		T70	22		-	-
auto[1]	values[1]	values[0]	52	1			T93	26		T82	26		-	-
auto[1]	values[1]	values[1]	12	1			T72	4		T349	8		-	-
auto[1]	values[1]	values[2]	30	1			T71	24		T350	6		-	-
auto[1]	values[1]	values[3]	8	1			T351	8		-	-		-	-
auto[1]	values[1]	values[5]	26	1			T237	26		-	-		-	-
auto[1]	values[2]	values[0]	12	1			T352	12		-	-		-	-
auto[1]	values[2]	values[2]	24	1			T198	24		-	-		-	-
auto[1]	values[2]	values[4]	32	1			T296	32		-	-		-	-
auto[1]	values[2]	values[5]	66	1			T267	32		T298	34		-	-
auto[1]	values[2]	values[7]	56	1			T280	32		T299	24		-	-
auto[1]	values[3]	values[0]	26	1			T77	26		-	-		-	-
auto[1]	values[3]	values[1]	12	1			T285	12		-	-		-	-
auto[1]	values[3]	values[2]	24	1			T78	24		-	-		-	-
auto[1]	values[3]	values[3]	16	1			T104	16		-	-		-	-
auto[1]	values[3]	values[4]	2	1			T353	2		-	-		-	-
auto[1]	values[3]	values[5]	8	1			T191	8		-	-		-	-
auto[1]	values[3]	values[7]	10	1			T224	10		-	-		-	-
auto[1]	values[4]	values[2]	10	1			T354	10		-	-		-	-
auto[1]	values[4]	values[6]	16	1			T80	16		-	-		-	-
auto[1]	values[5]	values[0]	44	1			T253	10		T83	32		T261	2
auto[1]	values[5]	values[5]	10	1			T355	10		-	-		-	-
auto[1]	values[5]	values[6]	14	1			T356	14		-	-		-	-
auto[1]	values[5]	values[7]	36	1			T194	34		T259	2		-	-
auto[1]	values[6]	values[0]	6	1			T254	6		-	-		-	-
auto[1]	values[6]	values[2]	10	1			T357	10		-	-		-	-
auto[1]	values[6]	values[3]	10	1			T81	4		T275	6		-	-
auto[1]	values[6]	values[4]	36	1			T245	36		-	-		-	-
auto[1]	values[6]	values[7]	14	1			T358	14		-	-		-	-
auto[1]	values[7]	values[0]	22	1			T276	22		-	-		-	-
auto[1]	values[7]	values[2]	38	1			T289	22		T297	16		-	-
auto[1]	values[7]	values[4]	22	1			T359	22		-	-		-	-
auto[1]	values[7]	values[6]	26	1			T91	6		T264	12		T79	8