Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	130	1			T4	4		T49	6		T44	6
auto[ReadAddrCrossIntoMailbox]	42	1			T196	2		T136	2		T293	4
auto[ReadAddrCrossOutOfMailbox]	36	1			T197	2		T243	2		T136	2
auto[ReadAddrCrossAllMailbox]	28	1			T196	2		T197	2		T136	2
auto[ReadAddrOutsideMailbox]	840	1			T9	4		T11	8		T43	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

538

1

T4

2

T9

2

T11

4

auto[1]

538

1

T4

2

T9

2

T11

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	198	1			T11	2		T75	4		T194	10
read_ops[0x0b]	184	1			T76	8		T49	2		T44	2
read_ops[0x3b]	222	1			T9	2		T43	4		T76	2
read_ops[0x6b]	124	1			T11	2		T75	4		T196	4
read_ops[0xbb]	174	1			T9	2		T11	2		T49	4
read_ops[0xeb]	174	1			T4	4		T11	2		T74	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	13	1			T241	3		T345	2		T209	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	13	1			T241	3		T345	2		T209	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	3	1			T293	1		T209	1		T336	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	3	1			T293	1		T209	1		T336	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	3	1			T197	1		T209	1		T336	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	3	1			T197	1		T209	1		T336	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	2	1			T94	2		-	-		-	-
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	2	1			T94	2		-	-		-	-
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	78	1			T11	1		T75	2		T194	5
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	78	1			T11	1		T75	2		T194	5
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	9	1			T49	1		T44	1		T103	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	9	1			T49	1		T44	1		T103	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	5	1			T201	2		T202	1		T336	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	5	1			T201	2		T202	1		T336	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	5	1			T293	1		T201	3		T202	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	5	1			T293	1		T201	3		T202	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	3	1			T202	1		T336	1		T94	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	3	1			T202	1		T336	1		T94	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	70	1			T76	4		T45	2		T130	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	70	1			T76	4		T45	2		T130	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	13	1			T89	1		T103	2		T218	3
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	13	1			T89	1		T103	2		T218	3
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	2	1			T136	1		T230	1		-	-
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	2	1			T136	1		T230	1		-	-
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	5	1			T136	1		T202	1		T230	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	5	1			T136	1		T202	1		T230	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	3	1			T136	1		T293	1		T206	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	3	1			T136	1		T293	1		T206	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	88	1			T9	1		T43	2		T76	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	88	1			T9	1		T43	2		T76	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	1	1			T117	1		-	-		-	-
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	1	1			T117	1		-	-		-	-
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	1	1			T196	1		-	-		-	-
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	1	1			T196	1		-	-		-	-
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	2	1			T243	1		T226	1		-	-
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	2	1			T243	1		T226	1		-	-
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	1	1			T196	1		-	-		-	-
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	1	1			T196	1		-	-		-	-
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	57	1			T11	1		T75	2		T225	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	57	1			T11	1		T75	2		T225	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	13	1			T49	2		T44	2		T103	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	13	1			T49	2		T44	2		T103	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	3	1			T202	1		T266	2		-	-
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	3	1			T202	1		T266	2		-	-
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	1	1			T201	1		-	-		-	-
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	1	1			T201	1		-	-		-	-
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	4	1			T197	1		T202	1		T336	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	4	1			T197	1		T202	1		T336	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	66	1			T9	1		T11	1		T75	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	66	1			T9	1		T11	1		T75	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	16	1			T4	2		T196	1		T117	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	16	1			T4	2		T196	1		T117	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	7	1			T293	1		T201	4		T94	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	7	1			T293	1		T201	4		T94	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	2	1			T201	1		T266	1		-	-
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	2	1			T201	1		T266	1		-	-
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	1	1			T293	1		-	-		-	-
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	1	1			T293	1		-	-		-	-
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	61	1			T11	1		T74	1		T225	3
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	61	1			T11	1		T74	1		T225	3