Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	253399	1			T1	1		T3	1		T7	304
all_pins[1]	253399	1			T1	1		T3	1		T7	304
all_pins[2]	253399	1			T1	1		T3	1		T7	304
all_pins[3]	253399	1			T1	1		T3	1		T7	304
all_pins[4]	253399	1			T1	1		T3	1		T7	304
all_pins[5]	253399	1			T1	1		T3	1		T7	304
all_pins[6]	253399	1			T1	1		T3	1		T7	304
all_pins[7]	253399	1			T1	1		T3	1		T7	304

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2026288	1			T1	8		T3	8		T7	2432
values[0x1]	904	1			T32	23		T33	25		T41	40
transitions[0x0=>0x1]	676	1			T32	20		T33	22		T41	27
transitions[0x1=>0x0]	683	1			T32	20		T33	22		T41	27

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	253303	1			T1	1		T3	1		T7	304
all_pins[0]	values[0x1]	96	1			T32	2		T33	3		T41	3
all_pins[0]	transitions[0x0=>0x1]	72	1			T32	2		T33	3		T41	1
all_pins[0]	transitions[0x1=>0x0]	101	1			T32	2		T33	4		T41	6
all_pins[1]	values[0x0]	253274	1			T1	1		T3	1		T7	304
all_pins[1]	values[0x1]	125	1			T32	2		T33	4		T41	8
all_pins[1]	transitions[0x0=>0x1]	107	1			T32	2		T33	4		T41	8
all_pins[1]	transitions[0x1=>0x0]	68	1			T32	3		T33	1		T41	5
all_pins[2]	values[0x0]	253313	1			T1	1		T3	1		T7	304
all_pins[2]	values[0x1]	86	1			T32	3		T33	1		T41	5
all_pins[2]	transitions[0x0=>0x1]	53	1			T32	3		T33	1		T41	3
all_pins[2]	transitions[0x1=>0x0]	92	1			T32	4		T33	2		T41	2
all_pins[3]	values[0x0]	253274	1			T1	1		T3	1		T7	304
all_pins[3]	values[0x1]	125	1			T32	4		T33	2		T41	4
all_pins[3]	transitions[0x0=>0x1]	84	1			T32	1		T33	2		T41	2
all_pins[3]	transitions[0x1=>0x0]	89	1			T32	1		T33	6		T41	3
all_pins[4]	values[0x0]	253269	1			T1	1		T3	1		T7	304
all_pins[4]	values[0x1]	130	1			T32	4		T33	6		T41	5
all_pins[4]	transitions[0x0=>0x1]	96	1			T32	4		T33	5		T41	1
all_pins[4]	transitions[0x1=>0x0]	94	1			T32	5		T33	3		T41	2
all_pins[5]	values[0x0]	253271	1			T1	1		T3	1		T7	304
all_pins[5]	values[0x1]	128	1			T32	5		T33	4		T41	6
all_pins[5]	transitions[0x0=>0x1]	108	1			T32	5		T33	3		T41	5
all_pins[5]	transitions[0x1=>0x0]	76	1			T33	3		T41	2		T177	1
all_pins[6]	values[0x0]	253303	1			T1	1		T3	1		T7	304
all_pins[6]	values[0x1]	96	1			T33	4		T41	3		T177	2
all_pins[6]	transitions[0x0=>0x1]	72	1			T33	3		T41	2		T373	1
all_pins[6]	transitions[0x1=>0x0]	94	1			T32	3		T41	5		T177	3
all_pins[7]	values[0x0]	253281	1			T1	1		T3	1		T7	304
all_pins[7]	values[0x1]	118	1			T32	3		T33	1		T41	6
all_pins[7]	transitions[0x0=>0x1]	84	1			T32	3		T33	1		T41	5
all_pins[7]	transitions[0x1=>0x0]	69	1			T32	2		T33	3		T41	2