Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
63.01	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	54	74	57.81

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	54	74	57.81	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	424	1			T99	8		T71	24		T69	4
values[1]	288	1			T9	12		T194	34		T28	8
values[2]	326	1			T45	32		T130	6		T74	16
values[3]	594	1			T11	22		T105	2		T195	30
values[4]	490	1			T6	4		T43	24		T98	6
values[5]	434	1			T76	24		T49	10		T196	6
values[6]	320	1			T4	6		T44	10		T197	4
values[7]	416	1			T8	6		T75	20		T104	16

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	464	1			T49	10		T75	20		T130	6
values[1]	352	1			T198	24		T192	26		T199	10
values[2]	346	1			T45	32		T27	22		T196	6
values[3]	246	1			T197	4		T57	4		T24	20
values[4]	602	1			T4	6		T6	4		T43	24
values[5]	352	1			T11	22		T28	8		T117	6
values[6]	434	1			T76	24		T99	8		T74	16
values[7]	496	1			T8	6		T9	12		T44	10

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3244

1

T4

6

T6

4

T8

6

auto[1]

48

1

T70

6

T72

2

T73

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	54	74	57.81	54

Automatically Generated Cross Bins for cr_all

Element holes

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[2] , values[3]]	*	--	--	16

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[values[5]]	0	1	1
[auto[0]]	[values[3]]	[values[6]]	0	1	1
[auto[1]]	[values[0]]	[values[0]]	0	1	1
[auto[1]]	[values[0]]	[values[2] , values[3] , values[4] , values[5] , values[6]]	--	--	5
[auto[1]]	[values[1]]	[values[1] , values[2] , values[3] , values[4] , values[5]]	--	--	5
[auto[1]]	[values[1]]	[values[7]]	0	1	1
[auto[1]]	[values[4]]	[values[2] , values[3]]	--	--	2
[auto[1]]	[values[4]]	[values[5]]	0	1	1
[auto[1]]	[values[4]]	[values[7]]	0	1	1
[auto[1]]	[values[5]]	[values[0] , values[1] , values[2] , values[3]]	--	--	4
[auto[1]]	[values[5]]	[values[5] , values[6] , values[7]]	--	--	3
[auto[1]]	[values[6]]	[values[0] , values[1] , values[2] , values[3] , values[4]]	--	--	5
[auto[1]]	[values[6]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[7]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[7]]	[values[3] , values[4] , values[5]]	--	--	3
[auto[1]]	[values[7]]	[values[7]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	46	1			T200	2		T201	28		T202	16
auto[0]	values[0]	values[1]	46	1			T199	10		T203	18		T77	18
auto[0]	values[0]	values[2]	56	1			T71	24		T106	18		T204	14
auto[0]	values[0]	values[3]	48	1			T24	20		T205	10		T206	18
auto[0]	values[0]	values[4]	58	1			T207	14		T208	22		T209	8
auto[0]	values[0]	values[6]	90	1			T99	8		T48	8		T210	28
auto[0]	values[0]	values[7]	62	1			T69	4		T72	2		T211	6
auto[0]	values[1]	values[0]	32	1			T212	20		T213	4		T81	2
auto[0]	values[1]	values[1]	14	1			T124	14		-	-		-	-
auto[0]	values[1]	values[2]	36	1			T214	16		T215	20		-	-
auto[0]	values[1]	values[3]	14	1			T216	2		T217	12		-	-
auto[0]	values[1]	values[4]	18	1			T136	8		T218	10		-	-
auto[0]	values[1]	values[5]	10	1			T28	8		T219	2		-	-
auto[0]	values[1]	values[6]	68	1			T220	22		T101	6		T83	30
auto[0]	values[1]	values[7]	92	1			T9	12		T194	34		T134	12
auto[0]	values[2]	values[0]	50	1			T130	6		T221	2		T222	16
auto[0]	values[2]	values[1]	12	1			T188	2		T223	10		-	-
auto[0]	values[2]	values[2]	86	1			T45	32		T27	22		T107	10
auto[0]	values[2]	values[3]	12	1			T123	2		T224	10		-	-
auto[0]	values[2]	values[4]	72	1			T225	12		T226	4		T227	10
auto[0]	values[2]	values[5]	26	1			T108	18		T228	8		-	-
auto[0]	values[2]	values[6]	26	1			T74	16		T229	6		T230	4
auto[0]	values[2]	values[7]	42	1			T231	10		T232	12		T233	20
auto[0]	values[3]	values[0]	120	1			T234	26		T235	10		T236	32
auto[0]	values[3]	values[1]	102	1			T192	26		T186	30		T237	26
auto[0]	values[3]	values[2]	36	1			T92	10		T238	14		T239	12
auto[0]	values[3]	values[3]	56	1			T240	18		T241	8		T242	2
auto[0]	values[3]	values[4]	132	1			T195	30		T243	12		T244	6
auto[0]	values[3]	values[5]	76	1			T11	22		T25	8		T245	36
auto[0]	values[3]	values[7]	72	1			T105	2		T246	6		T247	16
auto[0]	values[4]	values[0]	112	1			T29	12		T248	34		T249	26
auto[0]	values[4]	values[1]	100	1			T250	8		T73	24		T251	10
auto[0]	values[4]	values[2]	18	1			T131	4		T252	4		T253	10
auto[0]	values[4]	values[3]	38	1			T254	6		T255	12		T256	20
auto[0]	values[4]	values[4]	64	1			T6	4		T43	24		T80	14
auto[0]	values[4]	values[5]	52	1			T102	2		T257	22		T258	18
auto[0]	values[4]	values[6]	52	1			T135	14		T79	6		T259	2
auto[0]	values[4]	values[7]	44	1			T98	6		T193	14		T260	8
auto[0]	values[5]	values[0]	12	1			T49	10		T261	2		-	-
auto[0]	values[5]	values[1]	30	1			T262	6		T263	24		-	-
auto[0]	values[5]	values[2]	52	1			T196	6		T103	26		T264	12
auto[0]	values[5]	values[3]	40	1			T265	26		T266	14		-	-
auto[0]	values[5]	values[4]	118	1			T46	24		T70	16		T86	12
auto[0]	values[5]	values[5]	72	1			T117	6		T267	32		T268	34
auto[0]	values[5]	values[6]	54	1			T76	24		T269	8		T270	22
auto[0]	values[5]	values[7]	50	1			T47	14		T26	16		T271	2
auto[0]	values[6]	values[0]	26	1			T272	18		T273	8		-	-
auto[0]	values[6]	values[1]	24	1			T198	24		-	-		-	-
auto[0]	values[6]	values[2]	36	1			T274	30		T275	6		-	-
auto[0]	values[6]	values[3]	8	1			T197	4		T57	4		-	-
auto[0]	values[6]	values[4]	50	1			T4	6		T276	22		T277	22
auto[0]	values[6]	values[5]	82	1			T278	8		T279	8		T280	32
auto[0]	values[6]	values[6]	48	1			T281	10		T282	14		T94	14
auto[0]	values[6]	values[7]	42	1			T44	10		T118	16		T283	16
auto[0]	values[7]	values[0]	62	1			T75	20		T104	16		T284	6
auto[0]	values[7]	values[1]	12	1			T285	12		-	-		-	-
auto[0]	values[7]	values[2]	22	1			T286	2		T78	20		-	-
auto[0]	values[7]	values[3]	30	1			T287	12		T288	18		-	-
auto[0]	values[7]	values[4]	82	1			T89	2		T289	22		T191	8
auto[0]	values[7]	values[5]	30	1			T290	10		T291	20		-	-
auto[0]	values[7]	values[6]	90	1			T292	12		T293	20		T294	12
auto[0]	values[7]	values[7]	82	1			T8	6		T295	14		T184	12
auto[1]	values[0]	values[1]	8	1			T77	8		-	-		-	-
auto[1]	values[0]	values[7]	10	1			T72	2		T296	8		-	-
auto[1]	values[1]	values[0]	2	1			T81	2		-	-		-	-
auto[1]	values[1]	values[6]	2	1			T83	2		-	-		-	-
auto[1]	values[4]	values[0]	2	1			T297	2		-	-		-	-
auto[1]	values[4]	values[1]	4	1			T73	2		T298	2		-	-
auto[1]	values[4]	values[4]	2	1			T80	2		-	-		-	-
auto[1]	values[4]	values[6]	2	1			T79	2		-	-		-	-
auto[1]	values[5]	values[4]	6	1			T70	6		-	-		-	-
auto[1]	values[6]	values[5]	4	1			T299	4		-	-		-	-
auto[1]	values[7]	values[2]	4	1			T78	4		-	-		-	-
auto[1]	values[7]	values[6]	2	1			T82	2		-	-		-	-