SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 0 | 8 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_flip_position | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_opcode | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 140 | 1 | T5 | 5 | T12 | 11 | T96 | 2 | ||||
auto[1] | 117 | 1 | T5 | 4 | T12 | 11 | T96 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
read_ops[0x03] | 27 | 1 | T304 | 1 | T305 | 4 | T311 | 4 | ||||
read_ops[0x0b] | 52 | 1 | T5 | 2 | T12 | 9 | T96 | 3 | ||||
read_ops[0x3b] | 37 | 1 | T12 | 2 | T316 | 1 | T304 | 2 | ||||
read_ops[0x6b] | 21 | 1 | T12 | 2 | T97 | 2 | T364 | 2 | ||||
read_ops[0xbb] | 57 | 1 | T5 | 5 | T12 | 5 | T132 | 3 | ||||
read_ops[0xeb] | 63 | 1 | T5 | 2 | T12 | 4 | T372 | 5 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |