Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1293

1

T3

25

T15

2

T17

4

auto[1]

1275

1

T3

25

T15

2

T17

3

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

618

1

T18

16

T63

17

T64

15

auto[1]

1950

1

T3

50

T15

4

T17

7

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2322

1

T3

50

T15

4

T17

7

auto[1]

246

1

T18

7

T63

6

T64

7

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	537	1			T3	10		T15	2		T17	2
valid[1]	496	1			T3	17		T19	1		T20	3
valid[2]	526	1			T3	7		T17	2		T20	1
valid[3]	516	1			T3	4		T15	1		T17	3
valid[4]	493	1			T3	12		T15	1		T19	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	36	1			T18	1		T64	2		T84	2
auto[0]	auto[0]	valid[0]	auto[1]	207	1			T3	7		T19	1		T21	2
auto[0]	auto[0]	valid[1]	auto[0]	29	1			T18	1		T64	1		T65	1
auto[0]	auto[0]	valid[1]	auto[1]	179	1			T3	7		T18	2		T115	3
auto[0]	auto[0]	valid[2]	auto[0]	37	1			T18	1		T63	2		T64	1
auto[0]	auto[0]	valid[2]	auto[1]	203	1			T3	5		T17	2		T20	1
auto[0]	auto[0]	valid[3]	auto[0]	34	1			T18	2		T63	3		T66	1
auto[0]	auto[0]	valid[3]	auto[1]	196	1			T3	1		T15	1		T17	2
auto[0]	auto[0]	valid[4]	auto[0]	40	1			T63	2		T67	1		T84	1
auto[0]	auto[0]	valid[4]	auto[1]	194	1			T3	5		T15	1		T19	2
auto[0]	auto[1]	valid[0]	auto[0]	48	1			T18	1		T63	2		T64	1
auto[0]	auto[1]	valid[0]	auto[1]	187	1			T3	3		T15	2		T17	2
auto[0]	auto[1]	valid[1]	auto[0]	53	1			T18	2		T63	1		T64	1
auto[0]	auto[1]	valid[1]	auto[1]	190	1			T3	10		T19	1		T20	3
auto[0]	auto[1]	valid[2]	auto[0]	29	1			T63	1		T64	2		T84	1
auto[0]	auto[1]	valid[2]	auto[1]	207	1			T3	2		T63	2		T115	4
auto[0]	auto[1]	valid[3]	auto[0]	34	1			T18	1		T65	1		T68	1
auto[0]	auto[1]	valid[3]	auto[1]	199	1			T3	3		T17	1		T20	2
auto[0]	auto[1]	valid[4]	auto[0]	32	1			T66	1		T67	1		T68	2
auto[0]	auto[1]	valid[4]	auto[1]	188	1			T3	7		T20	1		T18	1
auto[1]	auto[0]	valid[0]	auto[0]	32	1			T18	1		T64	2		T66	1
auto[1]	auto[0]	valid[1]	auto[0]	25	1			T18	1		T64	1		T65	1
auto[1]	auto[0]	valid[2]	auto[0]	25	1			T63	3		T64	2		T65	1
auto[1]	auto[0]	valid[3]	auto[0]	33	1			T18	2		T63	1		T64	1
auto[1]	auto[0]	valid[4]	auto[0]	23	1			T68	1		T60	1		T383	1
auto[1]	auto[1]	valid[0]	auto[0]	27	1			T68	1		T391	2		T392	1
auto[1]	auto[1]	valid[1]	auto[0]	20	1			T18	1		T66	1		T84	1
auto[1]	auto[1]	valid[2]	auto[0]	25	1			T18	1		T65	1		T84	1
auto[1]	auto[1]	valid[3]	auto[0]	20	1			T18	1		T63	1		T65	2
auto[1]	auto[1]	valid[4]	auto[0]	16	1			T63	1		T64	1		T66	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal