Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16881

1

T7

16

T16

3

T18

504

auto[1]

19318

1

T3

620

T15

4

T17

7

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29908

1

T3

620

T7

6

T15

4

auto[1]

6291

1

T7

10

T16

2

T18

214

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	18792	1			T3	319		T7	9		T15	4
others[1]	3070	1			T3	56		T7	1		T20	7
others[2]	3070	1			T3	43		T7	1		T20	15
others[3]	3293	1			T3	56		T7	2		T20	12
interest[1]	1961	1			T3	42		T7	1		T16	1
interest[4]	12450	1			T3	201		T7	5		T15	4
interest[64]	6013	1			T3	104		T7	2		T20	20

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	5420	1			T7	3		T16	1		T18	162
auto[0]	auto[0]	others[1]	900	1			T7	1		T18	22		T62	1
auto[0]	auto[0]	others[2]	933	1			T18	27		T63	32		T64	17
auto[0]	auto[0]	others[3]	985	1			T7	2		T18	27		T62	1
auto[0]	auto[0]	interest[1]	569	1			T18	12		T63	20		T64	15
auto[0]	auto[0]	interest[4]	3561	1			T16	1		T18	107		T62	1
auto[0]	auto[0]	interest[64]	1783	1			T18	40		T62	1		T63	58
auto[0]	auto[1]	others[0]	10172	1			T3	319		T15	4		T17	7
auto[0]	auto[1]	others[1]	1624	1			T3	56		T20	7		T18	5
auto[0]	auto[1]	others[2]	1578	1			T3	43		T20	15		T18	12
auto[0]	auto[1]	others[3]	1755	1			T3	56		T20	12		T18	10
auto[0]	auto[1]	interest[1]	1033	1			T3	42		T20	10		T18	9
auto[0]	auto[1]	interest[4]	6782	1			T3	201		T15	4		T17	7
auto[0]	auto[1]	interest[64]	3156	1			T3	104		T20	20		T18	21
auto[1]	auto[0]	others[0]	3200	1			T7	6		T16	1		T18	116
auto[1]	auto[0]	others[1]	546	1			T18	19		T62	1		T63	21
auto[1]	auto[0]	others[2]	559	1			T7	1		T18	17		T62	1
auto[1]	auto[0]	others[3]	553	1			T18	18		T63	16		T64	13
auto[1]	auto[0]	interest[1]	359	1			T7	1		T16	1		T18	7
auto[1]	auto[0]	interest[4]	2107	1			T7	5		T16	1		T18	71
auto[1]	auto[0]	interest[64]	1074	1			T7	2		T18	37		T62	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal