Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	485	1			T32	18		T33	14		T41	21
all_values[1]	485	1			T32	18		T33	14		T41	21
all_values[2]	485	1			T32	18		T33	14		T41	21
all_values[3]	485	1			T32	18		T33	14		T41	21
all_values[4]	485	1			T32	18		T33	14		T41	21
all_values[5]	485	1			T32	18		T33	14		T41	21
all_values[6]	485	1			T32	18		T33	14		T41	21
all_values[7]	485	1			T32	18		T33	14		T41	21

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2047

1

T32

89

T33

44

T41

85

auto[1]

1833

1

T32

55

T33

68

T41

83

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1548

1

T32

64

T33

49

T41

70

auto[1]

2332

1

T32

80

T33

63

T41

98

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2227

1

T32

81

T33

63

T41

99

auto[1]

1653

1

T32

63

T33

49

T41

69

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	118	1			T32	9		T33	4		T41	5
all_values[0]	auto[0]	auto[0]	auto[1]	45	1			T41	2		T177	1		T373	2
all_values[0]	auto[0]	auto[1]	auto[0]	89	1			T32	3		T33	1		T41	7
all_values[0]	auto[0]	auto[1]	auto[1]	40	1			T32	1		T33	2		T41	1
all_values[0]	auto[1]	auto[0]	auto[1]	100	1			T32	4		T33	4		T41	2
all_values[0]	auto[1]	auto[1]	auto[1]	93	1			T32	1		T33	3		T41	4
all_values[1]	auto[0]	auto[0]	auto[0]	87	1			T32	6		T33	4		T41	2
all_values[1]	auto[0]	auto[0]	auto[1]	43	1			T41	1		T177	2		T373	1
all_values[1]	auto[0]	auto[1]	auto[0]	86	1			T32	6		T33	2		T41	6
all_values[1]	auto[0]	auto[1]	auto[1]	54	1			T32	1		T33	1		T41	4
all_values[1]	auto[1]	auto[0]	auto[1]	120	1			T32	4		T33	4		T41	5
all_values[1]	auto[1]	auto[1]	auto[1]	95	1			T32	1		T33	3		T41	3
all_values[2]	auto[0]	auto[0]	auto[0]	99	1			T32	2		T33	2		T41	6
all_values[2]	auto[0]	auto[0]	auto[1]	56	1			T32	1		T33	2		T41	2
all_values[2]	auto[0]	auto[1]	auto[0]	107	1			T32	3		T33	4		T41	1
all_values[2]	auto[0]	auto[1]	auto[1]	34	1			T41	3		T177	2		T373	2
all_values[2]	auto[1]	auto[0]	auto[1]	107	1			T32	6		T33	4		T41	7
all_values[2]	auto[1]	auto[1]	auto[1]	82	1			T32	6		T33	2		T41	2
all_values[3]	auto[0]	auto[0]	auto[0]	93	1			T32	6		T33	1		T41	2
all_values[3]	auto[0]	auto[0]	auto[1]	47	1			T32	1		T33	1		T41	4
all_values[3]	auto[0]	auto[1]	auto[0]	69	1			T32	1		T33	7		T41	4
all_values[3]	auto[0]	auto[1]	auto[1]	61	1			T32	2		T33	2		T41	2
all_values[3]	auto[1]	auto[0]	auto[1]	103	1			T32	3		T33	1		T41	6
all_values[3]	auto[1]	auto[1]	auto[1]	112	1			T32	5		T33	2		T41	3
all_values[4]	auto[0]	auto[0]	auto[0]	87	1			T32	3		T33	2		T41	4
all_values[4]	auto[0]	auto[0]	auto[1]	57	1			T32	3		T33	1		T41	1
all_values[4]	auto[0]	auto[1]	auto[0]	78	1			T32	3		T33	3		T41	6
all_values[4]	auto[0]	auto[1]	auto[1]	56	1			T32	2		T33	2		T41	1
all_values[4]	auto[1]	auto[0]	auto[1]	108	1			T32	6		T41	4		T177	1
all_values[4]	auto[1]	auto[1]	auto[1]	99	1			T32	1		T33	6		T41	5
all_values[5]	auto[0]	auto[0]	auto[0]	127	1			T32	6		T33	5		T41	5
all_values[5]	auto[0]	auto[1]	auto[0]	135	1			T32	3		T33	4		T41	5
all_values[5]	auto[1]	auto[0]	auto[1]	123	1			T32	4		T33	1		T41	6
all_values[5]	auto[1]	auto[1]	auto[1]	100	1			T32	5		T33	4		T41	5
all_values[6]	auto[0]	auto[0]	auto[0]	85	1			T32	4		T41	4		T177	1
all_values[6]	auto[0]	auto[0]	auto[1]	51	1			T32	2		T33	1		T41	2
all_values[6]	auto[0]	auto[1]	auto[0]	97	1			T32	2		T33	4		T41	4
all_values[6]	auto[0]	auto[1]	auto[1]	36	1			T33	1		T41	2		T177	1
all_values[6]	auto[1]	auto[0]	auto[1]	133	1			T32	9		T33	1		T41	6
all_values[6]	auto[1]	auto[1]	auto[1]	83	1			T32	1		T33	7		T41	3
all_values[7]	auto[0]	auto[0]	auto[0]	109	1			T32	7		T33	3		T41	4
all_values[7]	auto[0]	auto[0]	auto[1]	49	1			T32	1		T33	1		T41	2
all_values[7]	auto[0]	auto[1]	auto[0]	82	1			T33	3		T41	5		T373	2
all_values[7]	auto[0]	auto[1]	auto[1]	50	1			T32	3		T41	2		T177	1
all_values[7]	auto[1]	auto[0]	auto[1]	100	1			T32	2		T33	2		T41	3
all_values[7]	auto[1]	auto[1]	auto[1]	95	1			T32	5		T33	5		T41	5

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal