Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	252463	1			T3	1		T10	545		T11	1
all_values[1]	252463	1			T3	1		T10	545		T11	1
all_values[2]	252463	1			T3	1		T10	545		T11	1
all_values[3]	252463	1			T3	1		T10	545		T11	1
all_values[4]	252463	1			T3	1		T10	545		T11	1
all_values[5]	252463	1			T3	1		T10	545		T11	1
all_values[6]	252463	1			T3	1		T10	545		T11	1
all_values[7]	252463	1			T3	1		T10	545		T11	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2017638

1

T3

8

T10

4360

T11

8

auto[1]

2066

1

T35

41

T42

92

T43

65

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2017767

1

T3

8

T10

4359

T11

8

auto[1]

1937

1

T10

1

T17

4

T57

8

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	252093	1			T3	1		T10	545		T11	1
all_values[0]	auto[0]	auto[1]	113	1			T42	5		T43	2		T44	2
all_values[0]	auto[1]	auto[0]	146	1			T35	5		T42	8		T43	4
all_values[0]	auto[1]	auto[1]	111	1			T35	2		T42	1		T43	5
all_values[1]	auto[0]	auto[0]	252097	1			T3	1		T10	545		T11	1
all_values[1]	auto[0]	auto[1]	93	1			T35	1		T43	4		T44	5
all_values[1]	auto[1]	auto[0]	163	1			T35	1		T42	7		T43	6
all_values[1]	auto[1]	auto[1]	110	1			T35	1		T42	7		T43	4
all_values[2]	auto[0]	auto[0]	252096	1			T3	1		T10	545		T11	1
all_values[2]	auto[0]	auto[1]	98	1			T35	1		T42	6		T43	4
all_values[2]	auto[1]	auto[0]	166	1			T35	4		T42	12		T43	1
all_values[2]	auto[1]	auto[1]	103	1			T42	1		T43	1		T44	5
all_values[3]	auto[0]	auto[0]	252071	1			T3	1		T10	545		T11	1
all_values[3]	auto[0]	auto[1]	126	1			T35	3		T301	11		T42	1
all_values[3]	auto[1]	auto[0]	154	1			T35	2		T42	6		T43	10
all_values[3]	auto[1]	auto[1]	112	1			T35	3		T42	5		T43	1
all_values[4]	auto[0]	auto[0]	252081	1			T3	1		T10	545		T11	1
all_values[4]	auto[0]	auto[1]	125	1			T155	1		T35	1		T369	4
all_values[4]	auto[1]	auto[0]	149	1			T35	6		T42	3		T43	7
all_values[4]	auto[1]	auto[1]	108	1			T35	2		T42	1		T43	4
all_values[5]	auto[0]	auto[0]	251904	1			T3	1		T10	544		T11	1
all_values[5]	auto[0]	auto[1]	318	1			T10	1		T17	4		T57	8
all_values[5]	auto[1]	auto[0]	140	1			T35	8		T42	9		T43	5
all_values[5]	auto[1]	auto[1]	101	1			T35	1		T42	6		T43	5
all_values[6]	auto[0]	auto[0]	252121	1			T3	1		T10	545		T11	1
all_values[6]	auto[0]	auto[1]	99	1			T35	3		T42	4		T43	7
all_values[6]	auto[1]	auto[0]	141	1			T42	10		T43	4		T44	11
all_values[6]	auto[1]	auto[1]	102	1			T35	3		T43	2		T44	1
all_values[7]	auto[0]	auto[0]	252089	1			T3	1		T10	545		T11	1
all_values[7]	auto[0]	auto[1]	114	1			T35	3		T42	1		T43	5
all_values[7]	auto[1]	auto[0]	156	1			T35	1		T42	10		T43	6
all_values[7]	auto[1]	auto[1]	104	1			T35	2		T42	6		T44	1