Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
74.59	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	1	37	97.37
Crosses	84	30	54	64.29

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	1	1	50.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	27	21	43.75	100	1	1	0
cr_modeXdummyXnum_lanes	36	3	33	91.67	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	1144	1			T9	2		T5	8		T12	2
auto[SpiFlashAddrCfg]	928	1			T5	2		T7	2		T8	2
auto[SpiFlashAddr3b]	1138	1			T5	2		T6	4		T13	14
auto[SpiFlashAddr4b]	925	1			T5	14		T15	20		T61	4

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3177

1

T9

2

T5

26

T12

2

auto[1]

958

1

T62

30

T63

28

T64

10

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2220

1

T9

2

T5

10

T13

14

auto[1]

1915

1

T5

16

T12

2

T6

4

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1662	1			T9	2		T5	10		T12	2
values[1]	105	1			T62	4		T46	2		T63	4
values[2]	183	1			T15	4		T89	2		T85	7
values[3]	152	1			T5	8		T50	2		T48	2
values[4]	189	1			T15	4		T46	2		T178	6
values[5]	212	1			T13	11		T15	10		T50	2
values[6]	212	1			T5	2		T13	3		T63	8
values[7]	185	1			T61	2		T84	6		T77	6
values[8]	1235	1			T5	6		T6	4		T15	10

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3648

1

T9

2

T5

26

T12

2

auto[1]

487

1

T13

14

T84

16

T85

8

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

3974

1

T9

2

T5

26

T12

2

write

161

1

T61

10

T62

12

T63

4

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

1969

1

T9

2

T5

14

T6

4

valids[0x1]

2166

1

T5

12

T12

2

T13

11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	214	1			T5	4		T8	2		T15	2
internal_process_ops[0x5a]	170	1			T62	2		T46	2		T47	6
internal_process_ops[0x05]	192	1			T61	2		T89	2		T46	2
internal_process_ops[0x35]	190	1			T5	2		T12	2		T15	2
internal_process_ops[0x15]	180	1			T15	2		T46	2		T79	2
internal_process_ops[0x03]	296	1			T5	4		T7	2		T8	2
internal_process_ops[0x0b]	258	1			T5	2		T13	11		T155	6
internal_process_ops[0x3b]	263	1			T5	2		T15	4		T48	2
internal_process_ops[0x6b]	281	1			T15	10		T50	2		T84	1
internal_process_ops[0xbb]	273	1			T5	4		T15	10		T61	2
internal_process_ops[0xeb]	330	1			T6	4		T13	3		T15	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4067

1

T9

2

T5

26

T12

2

auto[1]

68

1

T62

12

T63

4

T65

8

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_upload

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4135

1

T9

2

T5

26

T12

2

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	27	21	43.75	27
Automatically Generated Cross Bins	48	27	21	43.75	27
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Element holes

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[write]	*	[auto[0]]	[auto[1]]	--	--	4
[auto[0]]	[write]	*	[auto[1]]	[auto[0]]	--	--	4
[auto[1]]	[read]	[auto[SpiFlashAddrDisabled]]	*	[auto[0]]	--	--	2
[auto[1]]	[write]	[auto[SpiFlashAddrDisabled] , auto[SpiFlashAddrCfg]]	*	*	--	--	8
[auto[1]]	[write]	[auto[SpiFlashAddr3b] , auto[SpiFlashAddr4b]]	[auto[1]]	*	--	--	4

Uncovered bins

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[read]	[auto[SpiFlashAddrCfg] , auto[SpiFlashAddr3b] , auto[SpiFlashAddr4b]]	[auto[1]]	[auto[0]]	--	--	3
[auto[1]]	[write]	[auto[SpiFlashAddr3b] , auto[SpiFlashAddr4b]]	[auto[0]]	[auto[1]]	--	--	2

Covered bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

914

1

T9

2

T5

8

T12

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

202

1

T63

2

T64

6

T225

10

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

530

1

T5

2

T7

2

T8

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

200

1

T62

2

T63

12

T64

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

642

1

T5

2

T6

4

T15

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

278

1

T62

10

T63

4

T64

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

520

1

T5

14

T15

20

T61

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

210

1

T62

6

T63

6

T225

18

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

22

1

T61

8

T228

6

T244

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

6

1

T65

2

T294

4

-

-

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

22

1

T209

4

T257

10

T239

8

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

22

1

T62

10

T70

4

T74

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

20

1

T67

6

T69

2

T202

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

26

1

T62

2

T63

4

T71

6

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

20

1

T61

2

T187

2

T277

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

14

1

T65

6

T292

4

T295

4

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

154

1

T84

12

T77

6

T155

7

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

168

1

T13

14

T84

4

T85

1

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

156

1

T85

7

T155

1

T156

8

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

4

1

T296

4

-

-

-

-

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

5

1

T107

5

-

-

-

-

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	3	33	91.67	3

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Uncovered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[1]]	[valids[0x0]]	0	1	1
[auto[1]]	[values[0] , values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	334	1			T9	2		T5	2		T8	2
auto[0]	values[0]	valids[0x1]	1272	1			T5	8		T12	2		T7	2
auto[0]	values[1]	valids[0x1]	96	1			T62	4		T46	2		T63	4
auto[0]	values[2]	valids[0x0]	84	1			T15	4		T89	2		T46	2
auto[0]	values[2]	valids[0x1]	60	1			T62	2		T29	4		T70	4
auto[0]	values[3]	valids[0x0]	102	1			T5	4		T50	2		T48	2
auto[0]	values[3]	valids[0x1]	30	1			T5	4		T244	2		T171	2
auto[0]	values[4]	valids[0x0]	94	1			T15	4		T46	2		T67	2
auto[0]	values[4]	valids[0x1]	56	1			T178	6		T261	8		T28	2
auto[0]	values[5]	valids[0x0]	132	1			T15	10		T50	2		T62	6
auto[0]	values[5]	valids[0x1]	42	1			T119	2		T70	4		T71	2
auto[0]	values[6]	valids[0x0]	106	1			T5	2		T63	8		T30	10
auto[0]	values[6]	valids[0x1]	56	1			T192	4		T72	6		T235	2
auto[0]	values[7]	valids[0x0]	82	1			T61	2		T90	2		T30	6
auto[0]	values[7]	valids[0x1]	64	1			T67	2		T176	2		T202	2
auto[0]	values[8]	valids[0x0]	718	1			T5	6		T6	4		T15	10
auto[0]	values[8]	valids[0x1]	320	1			T46	2		T47	10		T118	4
auto[1]	values[0]	valids[0x1]	56	1			T85	1		T297	4		T298	10
auto[1]	values[1]	valids[0x1]	9	1			T299	5		T300	4		-	-
auto[1]	values[2]	valids[0x0]	30	1			T85	7		T106	3		T301	4
auto[1]	values[2]	valids[0x1]	9	1			T155	6		T302	3		-	-
auto[1]	values[3]	valids[0x0]	16	1			T303	7		T107	3		T300	2
auto[1]	values[3]	valids[0x1]	4	1			T106	4		-	-		-	-
auto[1]	values[4]	valids[0x0]	36	1			T304	5		T305	2		T299	4
auto[1]	values[4]	valids[0x1]	3	1			T300	3		-	-		-	-
auto[1]	values[5]	valids[0x0]	10	1			T84	6		T155	2		T172	2
auto[1]	values[5]	valids[0x1]	28	1			T13	11		T158	9		T296	6
auto[1]	values[6]	valids[0x0]	40	1			T13	3		T156	3		T158	4
auto[1]	values[6]	valids[0x1]	10	1			T155	6		T306	4		-	-
auto[1]	values[7]	valids[0x0]	33	1			T84	6		T77	6		T156	5
auto[1]	values[7]	valids[0x1]	6	1			T307	6		-	-		-	-
auto[1]	values[8]	valids[0x0]	152	1			T84	4		T155	6		T158	11
auto[1]	values[8]	valids[0x1]	45	1			T156	3		T308	2		T301	5