Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
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Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
36.36 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv


Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 16 2 14 87.50
Crosses 72 54 18 25.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_busy_bit 2 1 1 50.00 100 1 1 2
cp_is_host_read 2 0 2 100.00 100 1 1 2
cp_other_status 8 0 8 100.00 100 1 1 8
cp_sw_read_while_csb_active 2 0 2 100.00 100 1 1 2
cp_wel_bit 2 1 1 50.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all_except_csb 64 48 16 25.00 100 1 1 0
cr_busyXwelXcsb 8 6 2 25.00 100 1 1 0


Summary for Variable cp_busy_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_busy_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1481405 1 T9 3 T5 513 T12 6962


Summary for Variable cp_is_host_read

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_is_host_read

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1377595 1 T9 3 T5 1 T12 6962
auto[1] 103810 1 T5 512 T46 266 T47 264


Summary for Variable cp_other_status

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 8 0 8 100.00


Automatically Generated Bins for cp_other_status

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:524287] 322863 1 T9 3 T5 513 T12 1556
auto[524288:1048575] 158342 1 T12 3 T13 149 T15 936
auto[1048576:1572863] 145916 1 T6 466 T13 99 T15 1564
auto[1572864:2097151] 196291 1 T6 281 T13 423 T15 960
auto[2097152:2621439] 176436 1 T12 1389 T6 525 T13 517
auto[2621440:3145727] 144988 1 T12 1339 T6 140 T13 207
auto[3145728:3670015] 157062 1 T12 2675 T6 2 T13 130
auto[3670016:4194303] 179507 1 T13 533 T15 1204 T50 381


Summary for Variable cp_sw_read_while_csb_active

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sw_read_while_csb_active

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 118981 1 T9 3 T5 513 T12 34
auto[1] 1362424 1 T12 6928 T6 1142 T13 1869


Summary for Variable cp_wel_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_wel_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1481405 1 T9 3 T5 513 T12 6962


Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 48 16 25.00 48


Automatically Generated Cross Bins for cr_all_except_csb

Element holes
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * * -- -- 16
[auto[1]] * * * -- -- 32


Covered bins
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0:524287] auto[0] 242605 1 T9 3 T5 1 T12 1556
auto[0] auto[0] auto[0:524287] auto[1] 80258 1 T5 512 T46 266 T47 264
auto[0] auto[0] auto[524288:1048575] auto[0] 154770 1 T12 3 T13 149 T15 936
auto[0] auto[0] auto[524288:1048575] auto[1] 3572 1 T82 5 T113 3 T66 1
auto[0] auto[0] auto[1048576:1572863] auto[0] 140548 1 T6 466 T13 99 T15 1564
auto[0] auto[0] auto[1048576:1572863] auto[1] 5368 1 T79 1642 T82 401 T113 1
auto[0] auto[0] auto[1572864:2097151] auto[0] 194080 1 T6 281 T13 423 T15 960
auto[0] auto[0] auto[1572864:2097151] auto[1] 2211 1 T82 252 T174 27 T175 331
auto[0] auto[0] auto[2097152:2621439] auto[0] 175430 1 T12 1389 T6 525 T13 517
auto[0] auto[0] auto[2097152:2621439] auto[1] 1006 1 T66 1 T91 1 T174 2
auto[0] auto[0] auto[2621440:3145727] auto[0] 139264 1 T12 1339 T6 140 T13 207
auto[0] auto[0] auto[2621440:3145727] auto[1] 5724 1 T66 37 T174 4485 T175 6
auto[0] auto[0] auto[3145728:3670015] auto[0] 152892 1 T12 2675 T6 2 T13 130
auto[0] auto[0] auto[3145728:3670015] auto[1] 4170 1 T82 3 T113 2 T66 611
auto[0] auto[0] auto[3670016:4194303] auto[0] 178006 1 T13 533 T15 1204 T50 381
auto[0] auto[0] auto[3670016:4194303] auto[1] 1501 1 T79 14 T113 568 T66 37


Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 6 2 25.00 6


Automatically Generated Cross Bins for cr_busyXwelXcsb

Element holes
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * -- -- 2
[auto[1]] * * -- -- 4


Covered bins
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 118981 1 T9 3 T5 513 T12 34
auto[0] auto[0] auto[1] 1362424 1 T12 6928 T6 1142 T13 1869

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