Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
78.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	31	97	75.78

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	31	97	75.78	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2690

1

T9

2

T5

26

T12

2

auto[1]

958

1

T62

30

T63

28

T64

10

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	518	1			T5	26		T61	18		T50	10
values[1]	608	1			T8	6		T47	28		T67	28
values[2]	346	1			T7	2		T48	10		T49	6
values[3]	458	1			T64	10		T203	28		T65	10
values[4]	464	1			T118	32		T26	2		T221	16
values[5]	402	1			T9	2		T46	18		T82	16
values[6]	562	1			T12	2		T6	4		T15	40
values[7]	290	1			T70	30		T253	12		T258	10

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	402	1			T8	6		T69	14		T221	16
values[1]	522	1			T63	28		T201	6		T261	24
values[2]	524	1			T9	2		T5	26		T6	4
values[3]	474	1			T12	2		T178	8		T90	2
values[4]	532	1			T61	18		T89	14		T46	18
values[5]	296	1			T48	10		T92	2		T64	10
values[6]	516	1			T62	30		T49	6		T260	6
values[7]	382	1			T7	2		T15	40		T47	28

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	31	97	75.78	31

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[3]]	[values[3] , values[4]]	--	--	2
[auto[0]]	[values[3]]	[values[7]]	0	1	1
[auto[0]]	[values[7]]	[values[7]]	0	1	1
[auto[1]]	[values[0]]	[values[1] , values[2] , values[3]]	--	--	3
[auto[1]]	[values[0]]	[values[7]]	0	1	1
[auto[1]]	[values[1]]	[values[1]]	0	1	1
[auto[1]]	[values[2]]	[values[1] , values[2] , values[3] , values[4]]	--	--	4
[auto[1]]	[values[2]]	[values[6]]	0	1	1
[auto[1]]	[values[3]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[3]]	[values[6]]	0	1	1
[auto[1]]	[values[4]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[4]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[5]]	[values[0]]	0	1	1
[auto[1]]	[values[5]]	[values[2]]	0	1	1
[auto[1]]	[values[5]]	[values[5] , values[6]]	--	--	2
[auto[1]]	[values[6]]	[values[0]]	0	1	1
[auto[1]]	[values[6]]	[values[7]]	0	1	1
[auto[1]]	[values[7]]	[values[3] , values[4]]	--	--	2
[auto[1]]	[values[7]]	[values[6] , values[7]]	--	--	2

Covered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	20	1			T179	18		T233	2		-	-
auto[0]	values[0]	values[1]	108	1			T201	6		T309	24		T310	2
auto[0]	values[0]	values[2]	76	1			T5	26		T50	10		T184	10
auto[0]	values[0]	values[3]	52	1			T274	2		T311	22		T239	28
auto[0]	values[0]	values[4]	68	1			T61	18		T228	38		T312	10
auto[0]	values[0]	values[5]	16	1			T212	14		T313	2		-	-
auto[0]	values[0]	values[6]	34	1			T260	6		T314	14		T315	6
auto[0]	values[0]	values[7]	78	1			T119	4		T202	14		T215	12
auto[0]	values[1]	values[0]	66	1			T8	6		T87	16		T316	4
auto[0]	values[1]	values[1]	50	1			T188	28		T185	12		T317	10
auto[0]	values[1]	values[2]	16	1			T236	6		T318	10		-	-
auto[0]	values[1]	values[3]	72	1			T90	2		T319	14		T288	30
auto[0]	values[1]	values[4]	32	1			T67	28		T83	4		-	-
auto[0]	values[1]	values[5]	58	1			T249	2		T320	8		T285	24
auto[0]	values[1]	values[6]	78	1			T250	32		T321	26		T252	20
auto[0]	values[1]	values[7]	44	1			T47	28		T322	14		T323	2
auto[0]	values[2]	values[0]	22	1			T289	8		T324	14		-	-
auto[0]	values[2]	values[1]	26	1			T261	24		T325	2		-	-
auto[0]	values[2]	values[2]	30	1			T287	30		-	-		-	-
auto[0]	values[2]	values[3]	18	1			T91	16		T326	2		-	-
auto[0]	values[2]	values[4]	54	1			T28	10		T168	2		T198	20
auto[0]	values[2]	values[5]	10	1			T48	10		-	-		-	-
auto[0]	values[2]	values[6]	66	1			T49	6		T180	8		T278	32
auto[0]	values[2]	values[7]	44	1			T7	2		T283	10		T327	2
auto[0]	values[3]	values[0]	24	1			T248	22		T328	2		-	-
auto[0]	values[3]	values[1]	136	1			T209	30		T243	4		T329	14
auto[0]	values[3]	values[2]	84	1			T174	12		T267	34		T330	24
auto[0]	values[3]	values[5]	14	1			T256	14		-	-		-	-
auto[0]	values[3]	values[6]	66	1			T203	28		T331	16		T189	4
auto[0]	values[4]	values[0]	72	1			T221	16		T166	16		T332	14
auto[0]	values[4]	values[1]	30	1			T175	20		T269	10		-	-
auto[0]	values[4]	values[2]	18	1			T280	16		T238	2		-	-
auto[0]	values[4]	values[3]	14	1			T333	6		T226	8		-	-
auto[0]	values[4]	values[4]	76	1			T118	32		T231	32		T334	12
auto[0]	values[4]	values[5]	40	1			T26	2		T187	16		T235	12
auto[0]	values[4]	values[6]	34	1			T335	2		T336	2		T337	30
auto[0]	values[4]	values[7]	40	1			T263	6		T338	16		T277	10
auto[0]	values[5]	values[0]	28	1			T69	14		T182	6		T190	8
auto[0]	values[5]	values[1]	42	1			T177	4		T339	36		T340	2
auto[0]	values[5]	values[2]	86	1			T9	2		T176	14		T68	6
auto[0]	values[5]	values[3]	78	1			T82	16		T66	16		T341	28
auto[0]	values[5]	values[4]	24	1			T46	18		T183	6		-	-
auto[0]	values[5]	values[5]	4	1			T216	4		-	-		-	-
auto[0]	values[5]	values[6]	36	1			T281	2		T342	16		T229	18
auto[0]	values[5]	values[7]	42	1			T29	26		T291	16		-	-
auto[0]	values[6]	values[0]	54	1			T240	2		T237	10		T257	10
auto[0]	values[6]	values[1]	58	1			T242	14		T251	10		T343	10
auto[0]	values[6]	values[2]	50	1			T6	4		T25	10		T115	20
auto[0]	values[6]	values[3]	14	1			T12	2		T178	8		T254	2
auto[0]	values[6]	values[4]	100	1			T89	14		T79	4		T171	8
auto[0]	values[6]	values[5]	30	1			T92	2		T88	12		T224	16
auto[0]	values[6]	values[6]	38	1			T113	10		T344	28		-	-
auto[0]	values[6]	values[7]	40	1			T15	40		-	-		-	-
auto[0]	values[7]	values[0]	32	1			T192	20		T27	4		T345	8
auto[0]	values[7]	values[1]	24	1			T206	24		-	-		-	-
auto[0]	values[7]	values[2]	12	1			T253	12		-	-		-	-
auto[0]	values[7]	values[3]	12	1			T346	12		-	-		-	-
auto[0]	values[7]	values[4]	26	1			T193	10		T347	16		-	-
auto[0]	values[7]	values[5]	4	1			T348	4		-	-		-	-
auto[0]	values[7]	values[6]	70	1			T258	10		T186	12		T259	8
auto[1]	values[0]	values[0]	18	1			T349	18		-	-		-	-
auto[1]	values[0]	values[4]	16	1			T279	16		-	-		-	-
auto[1]	values[0]	values[5]	2	1			T197	2		-	-		-	-
auto[1]	values[0]	values[6]	30	1			T62	30		-	-		-	-
auto[1]	values[1]	values[0]	2	1			T276	2		-	-		-	-
auto[1]	values[1]	values[2]	22	1			T75	22		-	-		-	-
auto[1]	values[1]	values[3]	54	1			T223	26		T72	28		-	-
auto[1]	values[1]	values[4]	26	1			T218	26		-	-		-	-
auto[1]	values[1]	values[5]	20	1			T293	20		-	-		-	-
auto[1]	values[1]	values[6]	38	1			T195	20		T350	18		-	-
auto[1]	values[1]	values[7]	30	1			T264	30		-	-		-	-
auto[1]	values[2]	values[0]	34	1			T73	24		T290	10		-	-
auto[1]	values[2]	values[5]	40	1			T204	22		T220	18		-	-
auto[1]	values[2]	values[7]	2	1			T230	2		-	-		-	-
auto[1]	values[3]	values[2]	44	1			T262	26		T294	8		T200	10
auto[1]	values[3]	values[3]	18	1			T292	18		-	-		-	-
auto[1]	values[3]	values[4]	34	1			T65	10		T74	24		-	-
auto[1]	values[3]	values[5]	10	1			T64	10		-	-		-	-
auto[1]	values[3]	values[7]	28	1			T71	28		-	-		-	-
auto[1]	values[4]	values[2]	40	1			T76	40		-	-		-	-
auto[1]	values[4]	values[3]	38	1			T213	10		T268	28		-	-
auto[1]	values[4]	values[4]	58	1			T255	26		T246	32		-	-
auto[1]	values[4]	values[5]	4	1			T351	4		-	-		-	-
auto[1]	values[5]	values[1]	6	1			T247	6		-	-		-	-
auto[1]	values[5]	values[3]	16	1			T227	16		-	-		-	-
auto[1]	values[5]	values[4]	6	1			T352	6		-	-		-	-
auto[1]	values[5]	values[7]	34	1			T225	34		-	-		-	-
auto[1]	values[6]	values[1]	28	1			T63	28		-	-		-	-
auto[1]	values[6]	values[2]	10	1			T353	10		-	-		-	-
auto[1]	values[6]	values[3]	88	1			T270	30		T275	30		T286	28
auto[1]	values[6]	values[4]	12	1			T199	12		-	-		-	-
auto[1]	values[6]	values[5]	14	1			T241	14		-	-		-	-
auto[1]	values[6]	values[6]	26	1			T214	24		T265	2		-	-
auto[1]	values[7]	values[0]	30	1			T295	30		-	-		-	-
auto[1]	values[7]	values[1]	14	1			T222	14		-	-		-	-
auto[1]	values[7]	values[2]	36	1			T245	30		T354	6		-	-
auto[1]	values[7]	values[5]	30	1			T70	30		-	-		-	-