Group : spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg
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Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 66 0 66 100.00
Crosses 128 0 128 100.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_filtered 2 0 2 100.00 100 1 1 2
cp_opcode 64 0 64 100.00 100 1 1 64


Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 128 0 128 100.00 100 1 1 0


Summary for Variable cp_filtered

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_filtered

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1824 1 T9 1 T5 13 T12 1
auto[1] 2311 1 T9 1 T5 13 T12 1



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 64 0 64 100.00


Automatically Generated Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:3] 304 1 T5 4 T7 2 T8 2
auto[4:7] 262 1 T25 6 T61 2 T89 2
auto[8:11] 272 1 T5 2 T13 11 T155 6
auto[12:15] 14 1 T64 2 T202 2 T65 2
auto[16:19] 24 1 T235 2 T241 4 T285 2
auto[20:23] 196 1 T15 2 T46 2 T79 2
auto[24:27] 14 1 T68 2 T72 2 T235 2
auto[28:31] 18 1 T46 2 T176 2 T179 2
auto[32:35] 26 1 T61 2 T194 2 T312 2
auto[36:39] 4 1 T71 2 T383 2 - -
auto[40:43] 44 1 T62 4 T67 6 T331 2
auto[44:47] 6 1 T189 2 T293 4 - -
auto[48:51] 18 1 T46 2 T65 2 T248 2
auto[52:55] 202 1 T5 2 T12 2 T15 2
auto[56:59] 297 1 T5 2 T15 4 T48 2
auto[60:63] 26 1 T62 10 T225 2 T227 6
auto[64:67] 32 1 T67 2 T29 2 T331 6
auto[68:71] 32 1 T67 4 T29 4 T203 2
auto[72:75] 10 1 T262 2 T263 2 T72 2
auto[76:79] 14 1 T231 8 T290 2 T314 2
auto[80:83] 50 1 T63 4 T203 4 T262 2
auto[84:87] 16 1 T61 2 T30 6 T255 2
auto[88:91] 180 1 T62 2 T46 2 T47 6
auto[92:95] 20 1 T62 6 T186 2 T279 6
auto[96:99] 10 1 T202 2 T204 2 T232 6
auto[100:103] 18 1 T68 2 T221 4 T231 2
auto[104:107] 301 1 T15 10 T50 2 T84 1
auto[108:111] 20 1 T202 2 T188 2 T75 4
auto[112:115] 20 1 T29 2 T220 2 T341 2
auto[116:119] 14 1 T263 2 T279 2 T248 2
auto[120:123] 18 1 T204 4 T73 2 T209 4
auto[124:127] 22 1 T203 2 T28 2 T262 6
auto[128:131] 12 1 T61 2 T187 2 T271 4
auto[132:135] 16 1 T171 2 T75 2 T217 4
auto[136:139] 22 1 T89 2 T29 2 T245 2
auto[140:143] 16 1 T89 2 T179 2 T244 2
auto[144:147] 22 1 T186 2 T166 2 T312 2
auto[148:151] 8 1 T228 6 T346 2 - -
auto[152:155] 46 1 T62 2 T202 2 T188 4
auto[156:159] 226 1 T5 8 T8 2 T15 2
auto[160:163] 22 1 T119 2 T228 4 T72 2
auto[164:167] 18 1 T228 4 T270 6 T252 2
auto[168:171] 24 1 T70 6 T209 4 T213 2
auto[172:175] 22 1 T47 2 T29 2 T70 2
auto[176:179] 14 1 T260 2 T71 4 T244 2
auto[180:183] 112 1 T9 2 T5 2 T89 2
auto[184:187] 289 1 T5 4 T15 10 T61 2
auto[188:191] 22 1 T46 2 T68 2 T287 2
auto[192:195] 16 1 T61 2 T67 4 T260 2
auto[196:199] 16 1 T64 2 T225 6 T223 2
auto[200:203] 34 1 T63 4 T331 2 T186 4
auto[204:207] 30 1 T8 2 T65 6 T71 4
auto[208:211] 14 1 T72 2 T220 2 T166 4
auto[212:215] 16 1 T223 4 T187 2 T188 2
auto[216:219] 22 1 T225 6 T262 4 T210 2
auto[220:223] 22 1 T5 2 T187 4 T209 6
auto[224:227] 20 1 T62 2 T176 2 T69 2
auto[228:231] 20 1 T61 6 T62 2 T220 2
auto[232:235] 398 1 T6 4 T13 3 T15 4
auto[236:239] 22 1 T29 2 T71 2 T287 6
auto[240:243] 32 1 T63 6 T232 6 T255 2
auto[244:247] 30 1 T46 2 T29 2 T319 6
auto[248:251] 20 1 T216 2 T341 6 T210 2
auto[252:255] 28 1 T69 2 T201 2 T221 2



Summary for Cross cr_all

Samples crossed: cp_opcode cp_filtered
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_opcodecp_filteredCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:3] auto[0] 112 1 T5 2 T7 1 T8 1
auto[0:3] auto[1] 192 1 T5 2 T7 1 T8 1
auto[4:7] auto[0] 131 1 T25 3 T61 1 T89 1
auto[4:7] auto[1] 131 1 T25 3 T61 1 T89 1
auto[8:11] auto[0] 99 1 T5 1 T118 3 T82 2
auto[8:11] auto[1] 173 1 T5 1 T13 11 T155 6
auto[12:15] auto[0] 7 1 T64 1 T202 1 T65 1
auto[12:15] auto[1] 7 1 T64 1 T202 1 T65 1
auto[16:19] auto[0] 12 1 T235 1 T241 2 T285 1
auto[16:19] auto[1] 12 1 T235 1 T241 2 T285 1
auto[20:23] auto[0] 98 1 T15 1 T46 1 T79 1
auto[20:23] auto[1] 98 1 T15 1 T46 1 T79 1
auto[24:27] auto[0] 7 1 T68 1 T72 1 T235 1
auto[24:27] auto[1] 7 1 T68 1 T72 1 T235 1
auto[28:31] auto[0] 9 1 T46 1 T176 1 T179 1
auto[28:31] auto[1] 9 1 T46 1 T176 1 T179 1
auto[32:35] auto[0] 13 1 T61 1 T194 1 T312 1
auto[32:35] auto[1] 13 1 T61 1 T194 1 T312 1
auto[36:39] auto[0] 2 1 T71 1 T383 1 - -
auto[36:39] auto[1] 2 1 T71 1 T383 1 - -
auto[40:43] auto[0] 22 1 T62 2 T67 3 T331 1
auto[40:43] auto[1] 22 1 T62 2 T67 3 T331 1
auto[44:47] auto[0] 3 1 T189 1 T293 2 - -
auto[44:47] auto[1] 3 1 T189 1 T293 2 - -
auto[48:51] auto[0] 9 1 T46 1 T65 1 T248 1
auto[48:51] auto[1] 9 1 T46 1 T65 1 T248 1
auto[52:55] auto[0] 101 1 T5 1 T12 1 T15 1
auto[52:55] auto[1] 101 1 T5 1 T12 1 T15 1
auto[56:59] auto[0] 109 1 T5 1 T15 2 T48 1
auto[56:59] auto[1] 188 1 T5 1 T15 2 T48 1
auto[60:63] auto[0] 13 1 T62 5 T225 1 T227 3
auto[60:63] auto[1] 13 1 T62 5 T225 1 T227 3
auto[64:67] auto[0] 16 1 T67 1 T29 1 T331 3
auto[64:67] auto[1] 16 1 T67 1 T29 1 T331 3
auto[68:71] auto[0] 16 1 T67 2 T29 2 T203 1
auto[68:71] auto[1] 16 1 T67 2 T29 2 T203 1
auto[72:75] auto[0] 5 1 T262 1 T263 1 T72 1
auto[72:75] auto[1] 5 1 T262 1 T263 1 T72 1
auto[76:79] auto[0] 7 1 T231 4 T290 1 T314 1
auto[76:79] auto[1] 7 1 T231 4 T290 1 T314 1
auto[80:83] auto[0] 25 1 T63 2 T203 2 T262 1
auto[80:83] auto[1] 25 1 T63 2 T203 2 T262 1
auto[84:87] auto[0] 8 1 T61 1 T30 3 T255 1
auto[84:87] auto[1] 8 1 T61 1 T30 3 T255 1
auto[88:91] auto[0] 90 1 T62 1 T46 1 T47 3
auto[88:91] auto[1] 90 1 T62 1 T46 1 T47 3
auto[92:95] auto[0] 10 1 T62 3 T186 1 T279 3
auto[92:95] auto[1] 10 1 T62 3 T186 1 T279 3
auto[96:99] auto[0] 5 1 T202 1 T204 1 T232 3
auto[96:99] auto[1] 5 1 T202 1 T204 1 T232 3
auto[100:103] auto[0] 9 1 T68 1 T221 2 T231 1
auto[100:103] auto[1] 9 1 T68 1 T221 2 T231 1
auto[104:107] auto[0] 109 1 T15 5 T50 1 T47 3
auto[104:107] auto[1] 192 1 T15 5 T50 1 T84 1
auto[108:111] auto[0] 10 1 T202 1 T188 1 T75 2
auto[108:111] auto[1] 10 1 T202 1 T188 1 T75 2
auto[112:115] auto[0] 10 1 T29 1 T220 1 T341 1
auto[112:115] auto[1] 10 1 T29 1 T220 1 T341 1
auto[116:119] auto[0] 7 1 T263 1 T279 1 T248 1
auto[116:119] auto[1] 7 1 T263 1 T279 1 T248 1
auto[120:123] auto[0] 9 1 T204 2 T73 1 T209 2
auto[120:123] auto[1] 9 1 T204 2 T73 1 T209 2
auto[124:127] auto[0] 11 1 T203 1 T28 1 T262 3
auto[124:127] auto[1] 11 1 T203 1 T28 1 T262 3
auto[128:131] auto[0] 6 1 T61 1 T187 1 T271 2
auto[128:131] auto[1] 6 1 T61 1 T187 1 T271 2
auto[132:135] auto[0] 8 1 T171 1 T75 1 T217 2
auto[132:135] auto[1] 8 1 T171 1 T75 1 T217 2
auto[136:139] auto[0] 11 1 T89 1 T29 1 T245 1
auto[136:139] auto[1] 11 1 T89 1 T29 1 T245 1
auto[140:143] auto[0] 8 1 T89 1 T179 1 T244 1
auto[140:143] auto[1] 8 1 T89 1 T179 1 T244 1
auto[144:147] auto[0] 11 1 T186 1 T166 1 T312 1
auto[144:147] auto[1] 11 1 T186 1 T166 1 T312 1
auto[148:151] auto[0] 4 1 T228 3 T346 1 - -
auto[148:151] auto[1] 4 1 T228 3 T346 1 - -
auto[152:155] auto[0] 23 1 T62 1 T202 1 T188 2
auto[152:155] auto[1] 23 1 T62 1 T202 1 T188 2
auto[156:159] auto[0] 113 1 T5 4 T8 1 T15 1
auto[156:159] auto[1] 113 1 T5 4 T8 1 T15 1
auto[160:163] auto[0] 11 1 T119 1 T228 2 T72 1
auto[160:163] auto[1] 11 1 T119 1 T228 2 T72 1
auto[164:167] auto[0] 9 1 T228 2 T270 3 T252 1
auto[164:167] auto[1] 9 1 T228 2 T270 3 T252 1
auto[168:171] auto[0] 12 1 T70 3 T209 2 T213 1
auto[168:171] auto[1] 12 1 T70 3 T209 2 T213 1
auto[172:175] auto[0] 11 1 T47 1 T29 1 T70 1
auto[172:175] auto[1] 11 1 T47 1 T29 1 T70 1
auto[176:179] auto[0] 7 1 T260 1 T71 2 T244 1
auto[176:179] auto[1] 7 1 T260 1 T71 2 T244 1
auto[180:183] auto[0] 56 1 T9 1 T5 1 T89 1
auto[180:183] auto[1] 56 1 T9 1 T5 1 T89 1
auto[184:187] auto[0] 109 1 T5 2 T15 5 T61 1
auto[184:187] auto[1] 180 1 T5 2 T15 5 T61 1
auto[188:191] auto[0] 11 1 T46 1 T68 1 T287 1
auto[188:191] auto[1] 11 1 T46 1 T68 1 T287 1
auto[192:195] auto[0] 8 1 T61 1 T67 2 T260 1
auto[192:195] auto[1] 8 1 T61 1 T67 2 T260 1
auto[196:199] auto[0] 8 1 T64 1 T225 3 T223 1
auto[196:199] auto[1] 8 1 T64 1 T225 3 T223 1
auto[200:203] auto[0] 17 1 T63 2 T331 1 T186 2
auto[200:203] auto[1] 17 1 T63 2 T331 1 T186 2
auto[204:207] auto[0] 15 1 T8 1 T65 3 T71 2
auto[204:207] auto[1] 15 1 T8 1 T65 3 T71 2
auto[208:211] auto[0] 7 1 T72 1 T220 1 T166 2
auto[208:211] auto[1] 7 1 T72 1 T220 1 T166 2
auto[212:215] auto[0] 8 1 T223 2 T187 1 T188 1
auto[212:215] auto[1] 8 1 T223 2 T187 1 T188 1
auto[216:219] auto[0] 11 1 T225 3 T262 2 T210 1
auto[216:219] auto[1] 11 1 T225 3 T262 2 T210 1
auto[220:223] auto[0] 11 1 T5 1 T187 2 T209 3
auto[220:223] auto[1] 11 1 T5 1 T187 2 T209 3
auto[224:227] auto[0] 10 1 T62 1 T176 1 T69 1
auto[224:227] auto[1] 10 1 T62 1 T176 1 T69 1
auto[228:231] auto[0] 10 1 T61 3 T62 1 T220 1
auto[228:231] auto[1] 10 1 T61 3 T62 1 T220 1
auto[232:235] auto[0] 149 1 T6 2 T15 2 T25 2
auto[232:235] auto[1] 249 1 T6 2 T13 3 T15 2
auto[236:239] auto[0] 11 1 T29 1 T71 1 T287 3
auto[236:239] auto[1] 11 1 T29 1 T71 1 T287 3
auto[240:243] auto[0] 16 1 T63 3 T232 3 T255 1
auto[240:243] auto[1] 16 1 T63 3 T232 3 T255 1
auto[244:247] auto[0] 15 1 T46 1 T29 1 T319 3
auto[244:247] auto[1] 15 1 T46 1 T29 1 T319 3
auto[248:251] auto[0] 10 1 T216 1 T341 3 T210 1
auto[248:251] auto[1] 10 1 T216 1 T341 3 T210 1
auto[252:255] auto[0] 14 1 T69 1 T201 1 T221 1
auto[252:255] auto[1] 14 1 T69 1 T201 1 T221 1

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