Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.26	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	2	58	96.67

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	2	58	96.67	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	150	1			T50	10		T118	6		T49	4
auto[ReadAddrCrossIntoMailbox]	34	1			T118	6		T215	2		T283	4
auto[ReadAddrCrossOutOfMailbox]	50	1			T118	8		T258	4		T335	2
auto[ReadAddrCrossAllMailbox]	46	1			T118	8		T258	2		T333	2
auto[ReadAddrOutsideMailbox]	916	1			T5	12		T6	4		T7	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

598

1

T5

6

T6

2

T7

1

auto[1]

598

1

T5

6

T6

2

T7

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	216	1			T5	4		T7	2		T8	2
read_ops[0x0b]	184	1			T5	2		T118	6		T82	4
read_ops[0x3b]	174	1			T5	2		T15	4		T48	2
read_ops[0x6b]	192	1			T15	10		T50	2		T47	6
read_ops[0xbb]	200	1			T5	4		T15	10		T61	2
read_ops[0xeb]	230	1			T6	4		T15	4		T50	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	2	58	96.67	2

Automatically Generated Cross Bins for cr_all

Element holes

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	NUMBER	STATUS
[read_ops[0x6b]]	[auto[ReadAddrCrossAllMailbox]]	*	--	--	2

Covered bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	16	1			T50	3		T87	1		T224	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	16	1			T50	3		T87	1		T224	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	3	1			T118	1		T377	1		T366	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	3	1			T118	1		T377	1		T366	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	3	1			T335	1		T184	1		T361	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	3	1			T335	1		T184	1		T361	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	2	1			T118	1		T361	1		-	-
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	2	1			T118	1		T361	1		-	-
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	84	1			T5	2		T7	1		T8	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	84	1			T5	2		T7	1		T8	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	12	1			T49	2		T224	1		T250	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	12	1			T49	2		T224	1		T250	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	3	1			T215	1		T311	1		T366	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	3	1			T215	1		T311	1		T366	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	3	1			T311	1		T205	2		-	-
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	3	1			T311	1		T205	2		-	-
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	7	1			T118	3		T250	1		T311	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	7	1			T118	3		T250	1		T311	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	67	1			T5	1		T82	2		T261	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	67	1			T5	1		T82	2		T261	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	15	1			T118	1		T87	3		T253	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	15	1			T118	1		T87	3		T253	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	4	1			T118	1		T250	1		T360	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	4	1			T118	1		T250	1		T360	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	4	1			T118	1		T258	1		T250	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	4	1			T118	1		T258	1		T250	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	2	1			T250	1		T360	1		-	-
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	2	1			T250	1		T360	1		-	-
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	62	1			T5	1		T15	2		T48	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	62	1			T5	1		T15	2		T48	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	9	1			T50	1		T118	2		T87	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	9	1			T50	1		T118	2		T87	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	3	1			T118	1		T250	1		T378	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	3	1			T118	1		T250	1		T378	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	6	1			T118	3		T240	1		T361	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	6	1			T118	3		T240	1		T361	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	78	1			T15	5		T47	3		T63	4
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	78	1			T15	5		T47	3		T63	4
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	11	1			T87	1		T224	2		T243	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	11	1			T87	1		T224	2		T243	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	2	1			T311	1		T108	1		-	-
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	2	1			T311	1		T108	1		-	-
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	3	1			T250	1		T108	1		T356	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	3	1			T250	1		T108	1		T356	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	5	1			T233	1		T311	1		T205	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	5	1			T233	1		T311	1		T205	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	79	1			T5	2		T15	5		T61	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	79	1			T5	2		T15	5		T61	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	12	1			T50	1		T253	1		T333	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	12	1			T50	1		T253	1		T333	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	2	1			T283	2		-	-		-	-
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	2	1			T283	2		-	-		-	-
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	6	1			T258	1		T250	3		T311	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	6	1			T258	1		T250	3		T311	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	7	1			T258	1		T333	1		T311	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	7	1			T258	1		T333	1		T311	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	88	1			T6	2		T15	2		T89	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	88	1			T6	2		T15	2		T89	1