Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	252463	1			T3	1		T10	545		T11	1
all_pins[1]	252463	1			T3	1		T10	545		T11	1
all_pins[2]	252463	1			T3	1		T10	545		T11	1
all_pins[3]	252463	1			T3	1		T10	545		T11	1
all_pins[4]	252463	1			T3	1		T10	545		T11	1
all_pins[5]	252463	1			T3	1		T10	545		T11	1
all_pins[6]	252463	1			T3	1		T10	545		T11	1
all_pins[7]	252463	1			T3	1		T10	545		T11	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2018853	1			T3	8		T10	4360		T11	8
values[0x1]	851	1			T35	14		T42	27		T43	22
transitions[0x0=>0x1]	626	1			T35	10		T42	24		T43	19
transitions[0x1=>0x0]	636	1			T35	10		T42	24		T43	19

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	252352	1			T3	1		T10	545		T11	1
all_pins[0]	values[0x1]	111	1			T35	2		T42	1		T43	5
all_pins[0]	transitions[0x0=>0x1]	88	1			T35	2		T42	1		T43	5
all_pins[0]	transitions[0x1=>0x0]	87	1			T35	1		T42	7		T43	4
all_pins[1]	values[0x0]	252353	1			T3	1		T10	545		T11	1
all_pins[1]	values[0x1]	110	1			T35	1		T42	7		T43	4
all_pins[1]	transitions[0x0=>0x1]	78	1			T35	1		T42	6		T43	4
all_pins[1]	transitions[0x1=>0x0]	71	1			T43	1		T44	5		T373	2
all_pins[2]	values[0x0]	252360	1			T3	1		T10	545		T11	1
all_pins[2]	values[0x1]	103	1			T42	1		T43	1		T44	5
all_pins[2]	transitions[0x0=>0x1]	73	1			T43	1		T44	2		T373	2
all_pins[2]	transitions[0x1=>0x0]	82	1			T35	3		T42	4		T43	1
all_pins[3]	values[0x0]	252351	1			T3	1		T10	545		T11	1
all_pins[3]	values[0x1]	112	1			T35	3		T42	5		T43	1
all_pins[3]	transitions[0x0=>0x1]	81	1			T35	2		T42	4		T43	1
all_pins[3]	transitions[0x1=>0x0]	77	1			T35	1		T43	4		T373	1
all_pins[4]	values[0x0]	252355	1			T3	1		T10	545		T11	1
all_pins[4]	values[0x1]	108	1			T35	2		T42	1		T43	4
all_pins[4]	transitions[0x0=>0x1]	87	1			T35	2		T42	1		T43	2
all_pins[4]	transitions[0x1=>0x0]	80	1			T35	1		T42	6		T43	3
all_pins[5]	values[0x0]	252362	1			T3	1		T10	545		T11	1
all_pins[5]	values[0x1]	101	1			T35	1		T42	6		T43	5
all_pins[5]	transitions[0x0=>0x1]	73	1			T42	6		T43	4		T44	4
all_pins[5]	transitions[0x1=>0x0]	74	1			T35	2		T43	1		T373	4
all_pins[6]	values[0x0]	252361	1			T3	1		T10	545		T11	1
all_pins[6]	values[0x1]	102	1			T35	3		T43	2		T44	1
all_pins[6]	transitions[0x0=>0x1]	78	1			T35	2		T43	2		T44	1
all_pins[6]	transitions[0x1=>0x0]	80	1			T35	1		T42	6		T44	1
all_pins[7]	values[0x0]	252359	1			T3	1		T10	545		T11	1
all_pins[7]	values[0x1]	104	1			T35	2		T42	6		T44	1
all_pins[7]	transitions[0x0=>0x1]	68	1			T35	1		T42	6		T44	1
all_pins[7]	transitions[0x1=>0x0]	85	1			T35	1		T42	1		T43	5