Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
63.70	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	53	75	58.59

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	53	75	58.59	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	358	1			T50	10		T82	16		T176	14
values[1]	496	1			T7	2		T15	40		T61	18
values[2]	468	1			T62	30		T46	18		T79	4
values[3]	504	1			T9	2		T12	2		T25	10
values[4]	398	1			T63	28		T70	30		T177	4
values[5]	576	1			T5	26		T48	10		T47	28
values[6]	444	1			T6	4		T8	6		T92	2
values[7]	404	1			T178	8		T118	32		T88	12

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	424	1			T7	2		T50	10		T29	26
values[1]	512	1			T25	10		T66	16		T179	18
values[2]	348	1			T12	2		T6	4		T48	10
values[3]	456	1			T15	40		T89	14		T47	28
values[4]	332	1			T61	18		T67	28		T119	4
values[5]	552	1			T9	2		T46	18		T63	28
values[6]	544	1			T8	6		T90	2		T82	16
values[7]	480	1			T5	26		T79	4		T178	8

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3580

1

T9

2

T5

26

T12

2

auto[1]

68

1

T62

12

T63

4

T65

8

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	53	75	58.59	53

Automatically Generated Cross Bins for cr_all

Element holes

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[3]]	*	--	--	8

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[values[1]]	0	1	1
[auto[0]]	[values[2]]	[values[3]]	0	1	1
[auto[0]]	[values[6]]	[values[5]]	0	1	1
[auto[1]]	[values[0]]	[values[1] , values[2] , values[3]]	--	--	3
[auto[1]]	[values[0]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[1]]	[values[0] , values[1] , values[2] , values[3] , values[4]]	--	--	5
[auto[1]]	[values[1]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[2]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[2]]	[values[3] , values[4] , values[5] , values[6] , values[7]]	--	--	5
[auto[1]]	[values[4]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[4]]	[values[3] , values[4]]	--	--	2
[auto[1]]	[values[4]]	[values[6]]	0	1	1
[auto[1]]	[values[5]]	[values[0] , values[1] , values[2] , values[3]]	--	--	4
[auto[1]]	[values[5]]	[values[5]]	0	1	1
[auto[1]]	[values[5]]	[values[7]]	0	1	1
[auto[1]]	[values[6]]	[values[0]]	0	1	1
[auto[1]]	[values[6]]	[values[2] , values[3] , values[4] , values[5]]	--	--	4
[auto[1]]	[values[7]]	[values[0]]	0	1	1
[auto[1]]	[values[7]]	[values[2] , values[3] , values[4] , values[5] , values[6] , values[7]]	--	--	6

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	80	1			T50	10		T176	14		T180	8
auto[0]	values[0]	values[2]	2	1			T181	2		-	-		-	-
auto[0]	values[0]	values[3]	12	1			T182	6		T183	6		-	-
auto[0]	values[0]	values[4]	56	1			T73	22		T184	10		T185	12
auto[0]	values[0]	values[5]	160	1			T186	12		T187	16		T188	28
auto[0]	values[0]	values[6]	30	1			T82	16		T189	4		T190	8
auto[0]	values[0]	values[7]	8	1			T191	8		-	-		-	-
auto[0]	values[1]	values[0]	64	1			T7	2		T192	20		T193	10
auto[0]	values[1]	values[1]	74	1			T66	16		T194	24		T195	20
auto[0]	values[1]	values[2]	30	1			T196	8		T197	2		T198	20
auto[0]	values[1]	values[3]	124	1			T15	40		T89	14		T69	14
auto[0]	values[1]	values[4]	18	1			T61	18		-	-		-	-
auto[0]	values[1]	values[5]	18	1			T199	8		T200	10		-	-
auto[0]	values[1]	values[6]	104	1			T201	6		T202	14		T203	28
auto[0]	values[1]	values[7]	60	1			T204	22		T205	14		T206	24
auto[0]	values[2]	values[0]	70	1			T29	26		T207	14		T208	30
auto[0]	values[2]	values[1]	74	1			T209	30		T86	4		T210	20
auto[0]	values[2]	values[2]	44	1			T62	18		T211	26		-	-
auto[0]	values[2]	values[4]	52	1			T67	28		T212	14		T213	10
auto[0]	values[2]	values[5]	52	1			T46	18		T28	10		T214	24
auto[0]	values[2]	values[6]	78	1			T90	2		T87	16		T215	12
auto[0]	values[2]	values[7]	86	1			T79	4		T30	32		T216	4
auto[0]	values[3]	values[0]	92	1			T217	34		T218	26		T219	8
auto[0]	values[3]	values[1]	88	1			T25	10		T179	18		T220	18
auto[0]	values[3]	values[2]	42	1			T12	2		T221	16		T222	14
auto[0]	values[3]	values[3]	48	1			T26	2		T223	26		T224	16
auto[0]	values[3]	values[4]	46	1			T119	4		T225	34		T226	8
auto[0]	values[3]	values[5]	88	1			T9	2		T227	16		T228	38
auto[0]	values[3]	values[6]	20	1			T229	18		T230	2		-	-
auto[0]	values[3]	values[7]	80	1			T64	10		T231	32		T232	30
auto[0]	values[4]	values[0]	24	1			T233	2		T234	22		-	-
auto[0]	values[4]	values[1]	50	1			T91	16		T235	12		T27	4
auto[0]	values[4]	values[2]	72	1			T70	26		T177	4		T236	6
auto[0]	values[4]	values[3]	40	1			T237	10		T238	2		T239	28
auto[0]	values[4]	values[4]	16	1			T240	2		T241	14		-	-
auto[0]	values[4]	values[5]	66	1			T63	24		T242	14		T243	4
auto[0]	values[4]	values[6]	72	1			T244	10		T245	30		T246	32
auto[0]	values[4]	values[7]	46	1			T247	6		T248	22		T75	18
auto[0]	values[5]	values[0]	40	1			T68	6		T249	2		T250	32
auto[0]	values[5]	values[1]	30	1			T251	10		T252	20		-	-
auto[0]	values[5]	values[2]	80	1			T48	10		T49	6		T253	12
auto[0]	values[5]	values[3]	122	1			T47	28		T254	2		T255	26
auto[0]	values[5]	values[4]	40	1			T65	2		T256	14		T257	10
auto[0]	values[5]	values[5]	38	1			T113	10		T258	10		T259	8
auto[0]	values[5]	values[6]	142	1			T260	6		T261	24		T262	26
auto[0]	values[5]	values[7]	74	1			T5	26		T263	6		T264	30
auto[0]	values[6]	values[0]	30	1			T265	2		T266	28		-	-
auto[0]	values[6]	values[1]	56	1			T71	22		T267	34		-	-
auto[0]	values[6]	values[2]	52	1			T6	4		T175	20		T268	28
auto[0]	values[6]	values[3]	96	1			T92	2		T269	10		T270	30
auto[0]	values[6]	values[4]	30	1			T271	22		T272	8		-	-
auto[0]	values[6]	values[6]	86	1			T8	6		T273	32		T76	38
auto[0]	values[6]	values[7]	82	1			T274	2		T174	12		T275	26
auto[0]	values[7]	values[0]	20	1			T171	8		T276	2		T277	10
auto[0]	values[7]	values[1]	126	1			T278	32		T279	16		T280	16
auto[0]	values[7]	values[2]	10	1			T281	2		T282	8		-	-
auto[0]	values[7]	values[3]	14	1			T283	10		T284	4		-	-
auto[0]	values[7]	values[4]	64	1			T88	12		T285	24		T286	28
auto[0]	values[7]	values[5]	118	1			T118	32		T287	30		T288	30
auto[0]	values[7]	values[6]	8	1			T289	8		-	-		-	-
auto[0]	values[7]	values[7]	36	1			T178	8		T290	10		T291	16
auto[1]	values[0]	values[0]	4	1			T292	4		-	-		-	-
auto[1]	values[0]	values[4]	2	1			T73	2		-	-		-	-
auto[1]	values[0]	values[5]	4	1			T74	2		T293	2		-	-
auto[1]	values[1]	values[5]	4	1			T199	4		-	-		-	-
auto[1]	values[2]	values[2]	12	1			T62	12		-	-		-	-
auto[1]	values[4]	values[2]	4	1			T70	4		-	-		-	-
auto[1]	values[4]	values[5]	4	1			T63	4		-	-		-	-
auto[1]	values[4]	values[7]	4	1			T75	4		-	-		-	-
auto[1]	values[5]	values[4]	8	1			T65	8		-	-		-	-
auto[1]	values[5]	values[6]	2	1			T72	2		-	-		-	-
auto[1]	values[6]	values[1]	6	1			T71	6		-	-		-	-
auto[1]	values[6]	values[6]	2	1			T76	2		-	-		-	-
auto[1]	values[6]	values[7]	4	1			T275	4		-	-		-	-
auto[1]	values[7]	values[1]	8	1			T294	4		T295	4		-	-