Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1534

1

T3

8

T10

1

T11

3

auto[1]

1445

1

T3

4

T11

1

T19

9

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

642

1

T10

1

T21

13

T22

7

auto[1]

2337

1

T3

12

T11

4

T19

29

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2737

1

T3

12

T11

4

T19

29

auto[1]

242

1

T10

1

T21

6

T22

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	569	1			T3	1		T11	1		T19	4
valid[1]	598	1			T3	3		T19	7		T21	4
valid[2]	574	1			T3	2		T19	5		T21	3
valid[3]	626	1			T3	3		T11	2		T19	5
valid[4]	612	1			T3	3		T10	1		T11	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	29	1			T21	2		T56	1		T392	1
auto[0]	auto[0]	valid[0]	auto[1]	253	1			T11	1		T19	3		T16	4
auto[0]	auto[0]	valid[1]	auto[0]	41	1			T21	1		T22	1		T58	1
auto[0]	auto[0]	valid[1]	auto[1]	249	1			T3	3		T19	4		T16	6
auto[0]	auto[0]	valid[2]	auto[0]	50	1			T22	2		T56	2		T80	2
auto[0]	auto[0]	valid[2]	auto[1]	221	1			T3	2		T19	4		T16	2
auto[0]	auto[0]	valid[3]	auto[0]	41	1			T22	1		T80	1		T422	1
auto[0]	auto[0]	valid[3]	auto[1]	242	1			T3	2		T11	1		T19	3
auto[0]	auto[0]	valid[4]	auto[0]	53	1			T22	1		T56	2		T57	3
auto[0]	auto[0]	valid[4]	auto[1]	232	1			T3	1		T11	1		T19	6
auto[0]	auto[1]	valid[0]	auto[0]	45	1			T22	1		T56	7		T80	3
auto[0]	auto[1]	valid[0]	auto[1]	195	1			T3	1		T19	1		T16	1
auto[0]	auto[1]	valid[1]	auto[0]	36	1			T56	2		T80	2		T100	1
auto[0]	auto[1]	valid[1]	auto[1]	218	1			T19	3		T16	3		T18	10
auto[0]	auto[1]	valid[2]	auto[0]	34	1			T21	2		T56	2		T101	1
auto[0]	auto[1]	valid[2]	auto[1]	227	1			T19	1		T22	1		T16	3
auto[0]	auto[1]	valid[3]	auto[0]	37	1			T21	2		T56	1		T80	2
auto[0]	auto[1]	valid[3]	auto[1]	257	1			T3	1		T11	1		T19	2
auto[0]	auto[1]	valid[4]	auto[0]	34	1			T80	2		T415	1		T101	1
auto[0]	auto[1]	valid[4]	auto[1]	243	1			T3	2		T19	2		T16	7
auto[1]	auto[0]	valid[0]	auto[0]	26	1			T56	3		T98	1		T100	1
auto[1]	auto[0]	valid[1]	auto[0]	24	1			T21	1		T22	1		T101	1
auto[1]	auto[0]	valid[2]	auto[0]	22	1			T21	1		T56	2		T98	1
auto[1]	auto[0]	valid[3]	auto[0]	27	1			T57	1		T422	1		T98	1
auto[1]	auto[0]	valid[4]	auto[0]	24	1			T10	1		T57	1		T98	1
auto[1]	auto[1]	valid[0]	auto[0]	21	1			T21	1		T56	1		T80	2
auto[1]	auto[1]	valid[1]	auto[0]	30	1			T21	2		T56	1		T415	2
auto[1]	auto[1]	valid[2]	auto[0]	20	1			T80	1		T98	2		T99	1
auto[1]	auto[1]	valid[3]	auto[0]	22	1			T21	1		T56	1		T101	1
auto[1]	auto[1]	valid[4]	auto[0]	26	1			T80	1		T101	1		T99	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal