Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15714

1

T10

7

T21

436

T22

232

auto[1]

22554

1

T3

12

T11

4

T19

367

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32562

1

T3

12

T10

5

T11

4

auto[1]

5706

1

T10

2

T21

137

T22

78

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	19832	1			T3	12		T10	4		T11	4
others[1]	3275	1			T19	42		T21	44		T22	31
others[2]	3084	1			T10	1		T19	31		T21	30
others[3]	3647	1			T10	1		T19	32		T21	52
interest[1]	2059	1			T19	19		T21	27		T22	17
interest[4]	13102	1			T3	12		T10	4		T11	4
interest[64]	6371	1			T10	1		T19	70		T21	65

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	5161	1			T10	4		T21	149		T22	74
auto[0]	auto[0]	others[1]	859	1			T21	33		T22	15		T17	1
auto[0]	auto[0]	others[2]	839	1			T21	20		T22	13		T56	38
auto[0]	auto[0]	others[3]	951	1			T10	1		T21	35		T22	22
auto[0]	auto[0]	interest[1]	551	1			T21	20		T22	8		T56	19
auto[0]	auto[0]	interest[4]	3357	1			T10	4		T21	104		T22	57
auto[0]	auto[0]	interest[64]	1647	1			T21	42		T22	22		T17	1
auto[0]	auto[1]	others[0]	11815	1			T3	12		T11	4		T19	173
auto[0]	auto[1]	others[1]	1922	1			T19	42		T22	9		T16	48
auto[0]	auto[1]	others[2]	1782	1			T19	31		T22	4		T16	33
auto[0]	auto[1]	others[3]	2147	1			T19	32		T22	5		T16	39
auto[0]	auto[1]	interest[1]	1183	1			T19	19		T22	2		T16	23
auto[0]	auto[1]	interest[4]	7846	1			T3	12		T11	4		T19	116
auto[0]	auto[1]	interest[64]	3705	1			T19	70		T22	5		T16	74
auto[1]	auto[0]	others[0]	2856	1			T21	69		T22	36		T17	7
auto[1]	auto[0]	others[1]	494	1			T21	11		T22	7		T55	1
auto[1]	auto[0]	others[2]	463	1			T10	1		T21	10		T22	6
auto[1]	auto[0]	others[3]	549	1			T21	17		T22	8		T17	2
auto[1]	auto[0]	interest[1]	325	1			T21	7		T22	7		T17	1
auto[1]	auto[0]	interest[4]	1899	1			T21	39		T22	23		T17	4
auto[1]	auto[0]	interest[64]	1019	1			T10	1		T21	23		T22	14

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal