Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	448	1			T35	10		T42	17		T43	14
all_values[1]	448	1			T35	10		T42	17		T43	14
all_values[2]	448	1			T35	10		T42	17		T43	14
all_values[3]	448	1			T35	10		T42	17		T43	14
all_values[4]	448	1			T35	10		T42	17		T43	14
all_values[5]	448	1			T35	10		T42	17		T43	14
all_values[6]	448	1			T35	10		T42	17		T43	14
all_values[7]	448	1			T35	10		T42	17		T43	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1902

1

T35

45

T42

74

T43

69

auto[1]

1682

1

T35

35

T42

62

T43

43

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1396

1

T35

37

T42

58

T43

46

auto[1]

2188

1

T35

43

T42

78

T43

66

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2016

1

T35

44

T42

74

T43

69

auto[1]

1568

1

T35

36

T42

62

T43

43

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	97	1			T35	2		T42	6		T43	4
all_values[0]	auto[0]	auto[0]	auto[1]	49	1			T42	2		T43	1		T44	3
all_values[0]	auto[0]	auto[1]	auto[0]	61	1			T35	3		T42	3		T43	2
all_values[0]	auto[0]	auto[1]	auto[1]	44	1			T43	3		T373	3		T374	2
all_values[0]	auto[1]	auto[0]	auto[1]	102	1			T42	5		T43	2		T44	1
all_values[0]	auto[1]	auto[1]	auto[1]	95	1			T35	5		T42	1		T43	2
all_values[1]	auto[0]	auto[0]	auto[0]	95	1			T35	5		T42	4		T43	5
all_values[1]	auto[0]	auto[0]	auto[1]	38	1			T43	1		T44	2		T373	1
all_values[1]	auto[0]	auto[1]	auto[0]	81	1			T42	3		T43	1		T44	1
all_values[1]	auto[0]	auto[1]	auto[1]	59	1			T35	1		T42	4		T43	4
all_values[1]	auto[1]	auto[0]	auto[1]	87	1			T35	3		T42	2		T43	3
all_values[1]	auto[1]	auto[1]	auto[1]	88	1			T35	1		T42	4		T44	2
all_values[2]	auto[0]	auto[0]	auto[0]	80	1			T35	5		T42	1		T43	5
all_values[2]	auto[0]	auto[0]	auto[1]	46	1			T42	2		T43	2		T44	3
all_values[2]	auto[0]	auto[1]	auto[0]	82	1			T35	1		T42	5		T44	3
all_values[2]	auto[0]	auto[1]	auto[1]	44	1			T44	2		T373	1		T375	1
all_values[2]	auto[1]	auto[0]	auto[1]	109	1			T35	4		T42	7		T43	6
all_values[2]	auto[1]	auto[1]	auto[1]	87	1			T42	2		T43	1		T44	2
all_values[3]	auto[0]	auto[0]	auto[0]	94	1			T35	2		T42	7		T43	3
all_values[3]	auto[0]	auto[0]	auto[1]	46	1			T42	1		T43	1		T44	2
all_values[3]	auto[0]	auto[1]	auto[0]	65	1			T35	1		T42	1		T43	4
all_values[3]	auto[0]	auto[1]	auto[1]	42	1			T35	2		T42	1		T44	2
all_values[3]	auto[1]	auto[0]	auto[1]	91	1			T35	2		T42	3		T43	3
all_values[3]	auto[1]	auto[1]	auto[1]	110	1			T35	3		T42	4		T43	3
all_values[4]	auto[0]	auto[0]	auto[0]	88	1			T35	3		T43	4		T44	5
all_values[4]	auto[0]	auto[0]	auto[1]	42	1			T35	1		T42	3		T44	3
all_values[4]	auto[0]	auto[1]	auto[0]	77	1			T35	3		T42	2		T43	1
all_values[4]	auto[0]	auto[1]	auto[1]	45	1			T43	2		T44	1		T373	2
all_values[4]	auto[1]	auto[0]	auto[1]	105	1			T35	2		T42	8		T43	2
all_values[4]	auto[1]	auto[1]	auto[1]	91	1			T35	1		T42	4		T43	5
all_values[5]	auto[0]	auto[0]	auto[0]	139	1			T42	7		T43	4		T44	3
all_values[5]	auto[0]	auto[1]	auto[0]	106	1			T35	8		T42	4		T43	3
all_values[5]	auto[1]	auto[0]	auto[1]	116	1			T35	1		T42	1		T43	2
all_values[5]	auto[1]	auto[1]	auto[1]	87	1			T35	1		T42	5		T43	5
all_values[6]	auto[0]	auto[0]	auto[0]	101	1			T35	1		T42	2		T43	2
all_values[6]	auto[0]	auto[0]	auto[1]	41	1			T35	1		T42	1		T43	5
all_values[6]	auto[0]	auto[1]	auto[0]	69	1			T42	5		T43	2		T44	6
all_values[6]	auto[0]	auto[1]	auto[1]	29	1			T373	1		T375	1		T376	1
all_values[6]	auto[1]	auto[0]	auto[1]	105	1			T35	6		T42	7		T43	3
all_values[6]	auto[1]	auto[1]	auto[1]	103	1			T35	2		T42	2		T43	2
all_values[7]	auto[0]	auto[0]	auto[0]	76	1			T35	1		T42	3		T43	5
all_values[7]	auto[0]	auto[0]	auto[1]	49	1			T35	2		T43	2		T373	1
all_values[7]	auto[0]	auto[1]	auto[0]	85	1			T35	2		T42	5		T43	1
all_values[7]	auto[0]	auto[1]	auto[1]	46	1			T42	2		T43	2		T375	1
all_values[7]	auto[1]	auto[0]	auto[1]	106	1			T35	4		T42	2		T43	4
all_values[7]	auto[1]	auto[1]	auto[1]	86	1			T35	1		T42	5		T44	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal