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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.11 97.55 92.91 98.61 80.85 95.97 90.90 87.98


Total test records in report: 857
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T770 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2667178649 May 07 01:15:36 PM PDT 24 May 07 01:15:38 PM PDT 24 12884942 ps
T144 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2092945424 May 07 01:15:11 PM PDT 24 May 07 01:15:15 PM PDT 24 137840660 ps
T125 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1583047907 May 07 01:15:03 PM PDT 24 May 07 01:15:05 PM PDT 24 20626983 ps
T129 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.4255801912 May 07 01:14:53 PM PDT 24 May 07 01:14:59 PM PDT 24 885744136 ps
T145 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1143006970 May 07 01:15:09 PM PDT 24 May 07 01:15:12 PM PDT 24 91912423 ps
T93 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3117733799 May 07 01:14:54 PM PDT 24 May 07 01:14:56 PM PDT 24 70501373 ps
T771 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3303546383 May 07 01:15:34 PM PDT 24 May 07 01:15:36 PM PDT 24 11615508 ps
T127 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1465050601 May 07 01:15:11 PM PDT 24 May 07 01:15:14 PM PDT 24 97663757 ps
T772 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2402275509 May 07 01:15:42 PM PDT 24 May 07 01:15:44 PM PDT 24 11232734 ps
T773 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.847415886 May 07 01:15:38 PM PDT 24 May 07 01:15:40 PM PDT 24 15362310 ps
T774 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1614553950 May 07 01:15:21 PM PDT 24 May 07 01:15:29 PM PDT 24 1156171976 ps
T94 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.4081528222 May 07 01:14:52 PM PDT 24 May 07 01:14:55 PM PDT 24 39848055 ps
T128 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1763251927 May 07 01:14:54 PM PDT 24 May 07 01:14:58 PM PDT 24 315855617 ps
T95 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1521361479 May 07 01:14:47 PM PDT 24 May 07 01:14:49 PM PDT 24 273585361 ps
T775 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1135910631 May 07 01:14:56 PM PDT 24 May 07 01:14:58 PM PDT 24 67363527 ps
T776 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1650296349 May 07 01:15:35 PM PDT 24 May 07 01:15:39 PM PDT 24 103844292 ps
T777 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1956112550 May 07 01:15:11 PM PDT 24 May 07 01:15:13 PM PDT 24 16929059 ps
T778 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2412816472 May 07 01:15:03 PM PDT 24 May 07 01:15:18 PM PDT 24 649084041 ps
T379 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2693663901 May 07 01:15:21 PM PDT 24 May 07 01:15:35 PM PDT 24 771311196 ps
T146 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3094559027 May 07 01:14:46 PM PDT 24 May 07 01:15:10 PM PDT 24 2188367330 ps
T779 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3833981666 May 07 01:14:52 PM PDT 24 May 07 01:14:54 PM PDT 24 30894214 ps
T147 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.270438155 May 07 01:15:28 PM PDT 24 May 07 01:15:30 PM PDT 24 73526345 ps
T148 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2377965135 May 07 01:15:20 PM PDT 24 May 07 01:15:22 PM PDT 24 66650068 ps
T780 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2858728527 May 07 01:15:36 PM PDT 24 May 07 01:15:38 PM PDT 24 39522004 ps
T781 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1324205213 May 07 01:15:35 PM PDT 24 May 07 01:15:37 PM PDT 24 14634579 ps
T782 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.639740167 May 07 01:15:29 PM PDT 24 May 07 01:15:32 PM PDT 24 48173214 ps
T131 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1544449403 May 07 01:15:22 PM PDT 24 May 07 01:15:27 PM PDT 24 61487333 ps
T783 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3562382415 May 07 01:15:42 PM PDT 24 May 07 01:15:43 PM PDT 24 22908467 ps
T784 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.759425003 May 07 01:15:28 PM PDT 24 May 07 01:15:32 PM PDT 24 77735813 ps
T149 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2397265280 May 07 01:15:38 PM PDT 24 May 07 01:15:41 PM PDT 24 656442506 ps
T785 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2305514071 May 07 01:15:36 PM PDT 24 May 07 01:15:38 PM PDT 24 44172844 ps
T786 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2788091489 May 07 01:15:00 PM PDT 24 May 07 01:15:15 PM PDT 24 1978486160 ps
T787 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2725588216 May 07 01:15:19 PM PDT 24 May 07 01:15:24 PM PDT 24 218638089 ps
T788 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.738848696 May 07 01:15:02 PM PDT 24 May 07 01:15:10 PM PDT 24 1991862757 ps
T789 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3409886490 May 07 01:15:10 PM PDT 24 May 07 01:15:15 PM PDT 24 56439947 ps
T790 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.716850276 May 07 01:15:20 PM PDT 24 May 07 01:15:25 PM PDT 24 766941961 ps
T791 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1905084956 May 07 01:15:03 PM PDT 24 May 07 01:15:05 PM PDT 24 30934712 ps
T792 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3416207231 May 07 01:15:19 PM PDT 24 May 07 01:15:22 PM PDT 24 245885141 ps
T793 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3017425718 May 07 01:14:52 PM PDT 24 May 07 01:14:57 PM PDT 24 1711541587 ps
T794 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.4076958650 May 07 01:15:29 PM PDT 24 May 07 01:15:32 PM PDT 24 308166465 ps
T795 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1827028530 May 07 01:15:27 PM PDT 24 May 07 01:15:29 PM PDT 24 41628554 ps
T380 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2354709219 May 07 01:15:12 PM PDT 24 May 07 01:15:30 PM PDT 24 7186673518 ps
T796 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1075703937 May 07 01:15:36 PM PDT 24 May 07 01:15:38 PM PDT 24 10455660 ps
T797 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3304676417 May 07 01:15:37 PM PDT 24 May 07 01:15:40 PM PDT 24 14103612 ps
T798 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3294080975 May 07 01:15:29 PM PDT 24 May 07 01:15:32 PM PDT 24 96217828 ps
T799 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3530739586 May 07 01:15:10 PM PDT 24 May 07 01:15:14 PM PDT 24 142688815 ps
T800 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.4210116906 May 07 01:15:35 PM PDT 24 May 07 01:15:37 PM PDT 24 13891130 ps
T801 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2446442287 May 07 01:15:11 PM PDT 24 May 07 01:15:14 PM PDT 24 14515363 ps
T802 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2189477435 May 07 01:15:36 PM PDT 24 May 07 01:15:38 PM PDT 24 37484758 ps
T803 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3579701755 May 07 01:15:02 PM PDT 24 May 07 01:15:04 PM PDT 24 33461043 ps
T804 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.443242227 May 07 01:15:19 PM PDT 24 May 07 01:15:24 PM PDT 24 620652136 ps
T805 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4200256164 May 07 01:14:47 PM PDT 24 May 07 01:14:49 PM PDT 24 211577763 ps
T806 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3030288841 May 07 01:15:26 PM PDT 24 May 07 01:15:29 PM PDT 24 318493381 ps
T807 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1595536168 May 07 01:15:28 PM PDT 24 May 07 01:15:32 PM PDT 24 997488115 ps
T808 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1007497584 May 07 01:15:01 PM PDT 24 May 07 01:15:04 PM PDT 24 50317966 ps
T809 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1243150330 May 07 01:15:37 PM PDT 24 May 07 01:15:39 PM PDT 24 43031936 ps
T810 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2938169107 May 07 01:15:35 PM PDT 24 May 07 01:15:40 PM PDT 24 133890453 ps
T132 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.27690447 May 07 01:15:27 PM PDT 24 May 07 01:15:32 PM PDT 24 172277521 ps
T811 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.285283898 May 07 01:14:48 PM PDT 24 May 07 01:14:53 PM PDT 24 423312185 ps
T812 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2638244921 May 07 01:15:19 PM PDT 24 May 07 01:15:21 PM PDT 24 22232127 ps
T813 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3625841194 May 07 01:14:57 PM PDT 24 May 07 01:15:04 PM PDT 24 777061365 ps
T814 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1012153339 May 07 01:15:20 PM PDT 24 May 07 01:15:29 PM PDT 24 120968949 ps
T815 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3180997020 May 07 01:14:55 PM PDT 24 May 07 01:15:00 PM PDT 24 160441690 ps
T816 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.4238519880 May 07 01:15:20 PM PDT 24 May 07 01:15:42 PM PDT 24 3749184416 ps
T817 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.700475580 May 07 01:15:12 PM PDT 24 May 07 01:15:15 PM PDT 24 12337862 ps
T818 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3946275095 May 07 01:15:11 PM PDT 24 May 07 01:15:15 PM PDT 24 81884249 ps
T382 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.667801074 May 07 01:14:45 PM PDT 24 May 07 01:14:59 PM PDT 24 1079972884 ps
T819 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.288917431 May 07 01:15:20 PM PDT 24 May 07 01:15:25 PM PDT 24 270324913 ps
T820 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.260158914 May 07 01:14:52 PM PDT 24 May 07 01:15:31 PM PDT 24 8581364249 ps
T821 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2361412537 May 07 01:15:12 PM PDT 24 May 07 01:15:34 PM PDT 24 607516756 ps
T822 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1257699635 May 07 01:15:36 PM PDT 24 May 07 01:15:38 PM PDT 24 21146009 ps
T823 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2076717953 May 07 01:14:53 PM PDT 24 May 07 01:15:15 PM PDT 24 331762695 ps
T824 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.4285190195 May 07 01:15:26 PM PDT 24 May 07 01:15:28 PM PDT 24 59984158 ps
T825 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1203369299 May 07 01:15:21 PM PDT 24 May 07 01:15:23 PM PDT 24 102644424 ps
T826 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.894846478 May 07 01:15:03 PM PDT 24 May 07 01:15:29 PM PDT 24 4790613746 ps
T827 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.4112547872 May 07 01:15:11 PM PDT 24 May 07 01:15:15 PM PDT 24 260153867 ps
T828 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1606353949 May 07 01:14:45 PM PDT 24 May 07 01:14:48 PM PDT 24 59269315 ps
T829 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2099268086 May 07 01:15:00 PM PDT 24 May 07 01:15:03 PM PDT 24 132405688 ps
T830 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1653530044 May 07 01:15:30 PM PDT 24 May 07 01:15:34 PM PDT 24 134944676 ps
T831 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.131216868 May 07 01:14:47 PM PDT 24 May 07 01:14:50 PM PDT 24 38804987 ps
T832 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3464496384 May 07 01:15:13 PM PDT 24 May 07 01:15:16 PM PDT 24 134576464 ps
T833 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.283630172 May 07 01:15:13 PM PDT 24 May 07 01:15:16 PM PDT 24 101777176 ps
T834 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3369864426 May 07 01:14:59 PM PDT 24 May 07 01:15:00 PM PDT 24 25912761 ps
T96 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.4215106903 May 07 01:14:52 PM PDT 24 May 07 01:14:55 PM PDT 24 41383020 ps
T835 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2466267566 May 07 01:15:25 PM PDT 24 May 07 01:15:27 PM PDT 24 15255852 ps
T836 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2123064571 May 07 01:15:11 PM PDT 24 May 07 01:15:31 PM PDT 24 2021937822 ps
T837 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2154417699 May 07 01:14:49 PM PDT 24 May 07 01:14:50 PM PDT 24 11441555 ps
T838 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3580239349 May 07 01:15:20 PM PDT 24 May 07 01:15:26 PM PDT 24 99396505 ps
T839 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.771834109 May 07 01:15:12 PM PDT 24 May 07 01:15:18 PM PDT 24 1172116874 ps
T840 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2858557665 May 07 01:15:11 PM PDT 24 May 07 01:15:14 PM PDT 24 77460999 ps
T841 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3450441366 May 07 01:14:48 PM PDT 24 May 07 01:14:50 PM PDT 24 25381715 ps
T842 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.399768419 May 07 01:14:54 PM PDT 24 May 07 01:14:55 PM PDT 24 29667529 ps
T843 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2161210848 May 07 01:15:35 PM PDT 24 May 07 01:15:41 PM PDT 24 433401820 ps
T844 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1989932805 May 07 01:15:12 PM PDT 24 May 07 01:15:18 PM PDT 24 560900893 ps
T845 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2072363997 May 07 01:15:36 PM PDT 24 May 07 01:15:39 PM PDT 24 56088477 ps
T846 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.955291331 May 07 01:15:11 PM PDT 24 May 07 01:15:13 PM PDT 24 34523267 ps
T847 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.412972982 May 07 01:15:11 PM PDT 24 May 07 01:15:15 PM PDT 24 53565400 ps
T848 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3730790594 May 07 01:15:36 PM PDT 24 May 07 01:15:38 PM PDT 24 23541739 ps
T849 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1686327537 May 07 01:15:36 PM PDT 24 May 07 01:15:38 PM PDT 24 14072579 ps
T850 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1656396850 May 07 01:15:36 PM PDT 24 May 07 01:15:38 PM PDT 24 17542047 ps
T851 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3100433447 May 07 01:15:19 PM PDT 24 May 07 01:15:21 PM PDT 24 28081410 ps
T852 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.702416659 May 07 01:15:34 PM PDT 24 May 07 01:15:40 PM PDT 24 661330765 ps
T853 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1453874518 May 07 01:15:11 PM PDT 24 May 07 01:15:17 PM PDT 24 204002741 ps
T854 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1792813682 May 07 01:15:06 PM PDT 24 May 07 01:15:15 PM PDT 24 1549824905 ps
T855 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1300553553 May 07 01:15:19 PM PDT 24 May 07 01:15:23 PM PDT 24 79715660 ps
T856 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4047164547 May 07 01:14:53 PM PDT 24 May 07 01:14:55 PM PDT 24 33112845 ps
T857 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3645486470 May 07 01:15:22 PM PDT 24 May 07 01:15:24 PM PDT 24 21667790 ps

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.762350591
Short name T9
Test name
Test status
Simulation time 198389577 ps
CPU time 2.38 seconds
Started May 07 01:24:13 PM PDT 24
Finished May 07 01:24:18 PM PDT 24
Peak memory 222292 kb
Host smart-15017aa7-0fd6-40f6-8672-889d5d07956f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762350591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.762350591
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1875960100
Short name T21
Test name
Test status
Simulation time 2370454467 ps
CPU time 26.21 seconds
Started May 07 01:23:31 PM PDT 24
Finished May 07 01:23:58 PM PDT 24
Peak memory 216228 kb
Host smart-f8bbfe67-17d6-4e41-a95d-c563d1ce9657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875960100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1875960100
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_intercept.661201613
Short name T15
Test name
Test status
Simulation time 2047584622 ps
CPU time 23.48 seconds
Started May 07 01:25:13 PM PDT 24
Finished May 07 01:25:37 PM PDT 24
Peak memory 221600 kb
Host smart-805679e4-40f7-455a-99f5-45f7a1e47b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661201613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.661201613
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1230683763
Short name T117
Test name
Test status
Simulation time 2521305586 ps
CPU time 20.2 seconds
Started May 07 01:15:29 PM PDT 24
Finished May 07 01:15:50 PM PDT 24
Peak memory 216288 kb
Host smart-798566a5-93d4-409e-a94c-8536521669e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230683763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1230683763
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2465913287
Short name T98
Test name
Test status
Simulation time 3532749301 ps
CPU time 26.99 seconds
Started May 07 01:23:59 PM PDT 24
Finished May 07 01:24:27 PM PDT 24
Peak memory 216132 kb
Host smart-74ecbefd-e114-45e6-abc4-8a72798691e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465913287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2465913287
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.774731170
Short name T88
Test name
Test status
Simulation time 43412624415 ps
CPU time 59.52 seconds
Started May 07 01:24:05 PM PDT 24
Finished May 07 01:25:07 PM PDT 24
Peak memory 232532 kb
Host smart-a2ad37c4-c6c1-4cc8-b39c-962918901113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774731170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.774731170
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.4110916229
Short name T43
Test name
Test status
Simulation time 388180194 ps
CPU time 0.94 seconds
Started May 07 01:24:45 PM PDT 24
Finished May 07 01:24:48 PM PDT 24
Peak memory 206456 kb
Host smart-3c4d3f9f-8923-423b-b1dc-b2037e984632
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110916229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.4110916229
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.4208893735
Short name T22
Test name
Test status
Simulation time 5115724783 ps
CPU time 25.85 seconds
Started May 07 01:24:23 PM PDT 24
Finished May 07 01:24:51 PM PDT 24
Peak memory 216200 kb
Host smart-2729d436-4fba-4634-8634-aff085e8f1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208893735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.4208893735
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.223063317
Short name T69
Test name
Test status
Simulation time 3014895093 ps
CPU time 5.65 seconds
Started May 07 01:24:25 PM PDT 24
Finished May 07 01:24:33 PM PDT 24
Peak memory 232232 kb
Host smart-98333bbc-32fa-4033-8958-7999e97e720c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223063317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.223063317
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_upload.2647834062
Short name T5
Test name
Test status
Simulation time 9574799677 ps
CPU time 31.34 seconds
Started May 07 01:24:31 PM PDT 24
Finished May 07 01:25:04 PM PDT 24
Peak memory 232584 kb
Host smart-26f4b860-8574-47dc-bbf5-005eec70f7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647834062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2647834062
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3077562791
Short name T399
Test name
Test status
Simulation time 16252978542 ps
CPU time 35.2 seconds
Started May 07 01:23:49 PM PDT 24
Finished May 07 01:24:27 PM PDT 24
Peak memory 216176 kb
Host smart-eda8f91d-47a0-4516-bcec-d00c230f3828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077562791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3077562791
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.594798986
Short name T45
Test name
Test status
Simulation time 19962621 ps
CPU time 0.78 seconds
Started May 07 01:23:00 PM PDT 24
Finished May 07 01:23:02 PM PDT 24
Peak memory 215864 kb
Host smart-8c053891-f6da-405b-97f9-92db2e00633e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594798986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.594798986
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.1536864204
Short name T25
Test name
Test status
Simulation time 294360119 ps
CPU time 3.88 seconds
Started May 07 01:24:24 PM PDT 24
Finished May 07 01:24:30 PM PDT 24
Peak memory 223744 kb
Host smart-ea658d7b-475d-4947-af49-8ff3ef5b10b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536864204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1536864204
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_intercept.417524781
Short name T91
Test name
Test status
Simulation time 482822304 ps
CPU time 4.83 seconds
Started May 07 01:23:52 PM PDT 24
Finished May 07 01:24:00 PM PDT 24
Peak memory 216640 kb
Host smart-a9bcab1b-73f5-46d2-aa5e-e6e102f1eb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417524781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.417524781
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1146359736
Short name T84
Test name
Test status
Simulation time 3369469765 ps
CPU time 20.72 seconds
Started May 07 01:23:10 PM PDT 24
Finished May 07 01:23:32 PM PDT 24
Peak memory 248996 kb
Host smart-529410ec-cd73-49b4-a790-85671d31bc23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146359736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1146359736
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2895449411
Short name T121
Test name
Test status
Simulation time 264592760 ps
CPU time 5.01 seconds
Started May 07 01:15:19 PM PDT 24
Finished May 07 01:15:24 PM PDT 24
Peak memory 216664 kb
Host smart-339ec5d3-610c-4130-8b12-4a6b2dea5cce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895449411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2895449411
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.427168066
Short name T389
Test name
Test status
Simulation time 7752349748 ps
CPU time 44.13 seconds
Started May 07 01:25:01 PM PDT 24
Finished May 07 01:25:46 PM PDT 24
Peak memory 216112 kb
Host smart-38ae61fd-45c6-485f-a32a-e6ba1349a981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427168066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.427168066
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3061428316
Short name T62
Test name
Test status
Simulation time 5602518438 ps
CPU time 18.35 seconds
Started May 07 01:24:18 PM PDT 24
Finished May 07 01:24:38 PM PDT 24
Peak memory 239404 kb
Host smart-c83f8ebe-0556-400b-a5bd-01de48bf484a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061428316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3061428316
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.180999799
Short name T118
Test name
Test status
Simulation time 36148291740 ps
CPU time 84.07 seconds
Started May 07 01:24:37 PM PDT 24
Finished May 07 01:26:02 PM PDT 24
Peak memory 240200 kb
Host smart-369bb98d-8284-44d9-90f8-bff034247090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180999799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.180999799
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3682941810
Short name T1
Test name
Test status
Simulation time 487834790 ps
CPU time 1.23 seconds
Started May 07 01:23:17 PM PDT 24
Finished May 07 01:23:19 PM PDT 24
Peak memory 236568 kb
Host smart-3a995cfb-f104-4167-a641-6f0761c4fac7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682941810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3682941810
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3230537500
Short name T72
Test name
Test status
Simulation time 519544136 ps
CPU time 7.38 seconds
Started May 07 01:23:48 PM PDT 24
Finished May 07 01:23:57 PM PDT 24
Peak memory 218220 kb
Host smart-110babe9-ca8a-4ad8-9dd2-aef071339bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230537500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3230537500
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_upload.1125987296
Short name T29
Test name
Test status
Simulation time 34521188077 ps
CPU time 39.18 seconds
Started May 07 01:25:09 PM PDT 24
Finished May 07 01:25:50 PM PDT 24
Peak memory 233076 kb
Host smart-fdb28cd3-40f7-4a1e-82d6-24165e11f0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125987296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1125987296
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2010803474
Short name T137
Test name
Test status
Simulation time 132432746 ps
CPU time 1.23 seconds
Started May 07 01:15:20 PM PDT 24
Finished May 07 01:15:22 PM PDT 24
Peak memory 215324 kb
Host smart-b0226880-2046-4dc6-9dc2-d0952269450c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010803474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2010803474
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.199918238
Short name T61
Test name
Test status
Simulation time 762454309 ps
CPU time 10.77 seconds
Started May 07 01:23:39 PM PDT 24
Finished May 07 01:23:51 PM PDT 24
Peak memory 245732 kb
Host smart-fe884383-dc41-423f-9e3e-06c2c717e209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199918238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.199918238
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.848607479
Short name T267
Test name
Test status
Simulation time 33053719945 ps
CPU time 23.03 seconds
Started May 07 01:24:12 PM PDT 24
Finished May 07 01:24:38 PM PDT 24
Peak memory 234520 kb
Host smart-26970d5d-d579-4f54-b07c-a7752fec63c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848607479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.848607479
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1626483054
Short name T311
Test name
Test status
Simulation time 6038953680 ps
CPU time 64.88 seconds
Started May 07 01:23:50 PM PDT 24
Finished May 07 01:24:58 PM PDT 24
Peak memory 232552 kb
Host smart-49349fba-4a15-4775-9861-3fa489a7104b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626483054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1626483054
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3105138214
Short name T71
Test name
Test status
Simulation time 17758441837 ps
CPU time 19.17 seconds
Started May 07 01:24:45 PM PDT 24
Finished May 07 01:25:07 PM PDT 24
Peak memory 236316 kb
Host smart-1eaea44f-2d92-495b-b4ab-b0c5e8c05e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105138214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3105138214
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2548166514
Short name T202
Test name
Test status
Simulation time 108799848 ps
CPU time 3.57 seconds
Started May 07 01:23:51 PM PDT 24
Finished May 07 01:23:57 PM PDT 24
Peak memory 222572 kb
Host smart-094b8333-eca3-42f6-a2ab-7abb29e97be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548166514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2548166514
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3603148130
Short name T73
Test name
Test status
Simulation time 1427732305 ps
CPU time 9.5 seconds
Started May 07 01:23:28 PM PDT 24
Finished May 07 01:23:38 PM PDT 24
Peak memory 223992 kb
Host smart-fc5b492d-49d9-4cf4-af0f-fee390db9110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603148130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3603148130
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.444154615
Short name T104
Test name
Test status
Simulation time 24215753927 ps
CPU time 20.27 seconds
Started May 07 01:23:01 PM PDT 24
Finished May 07 01:23:23 PM PDT 24
Peak memory 216136 kb
Host smart-7058a1b0-f9f8-40c1-9a88-c735b3174ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444154615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.444154615
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.3225792304
Short name T36
Test name
Test status
Simulation time 51828579 ps
CPU time 1.04 seconds
Started May 07 01:23:12 PM PDT 24
Finished May 07 01:23:14 PM PDT 24
Peak memory 216496 kb
Host smart-e7908c91-5743-42d8-a1b7-7795f0a79505
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225792304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.3225792304
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2010298577
Short name T248
Test name
Test status
Simulation time 5077862022 ps
CPU time 10.88 seconds
Started May 07 01:24:26 PM PDT 24
Finished May 07 01:24:39 PM PDT 24
Peak memory 216560 kb
Host smart-68395ef6-5540-4425-8b59-c3cfe6d93732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010298577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2010298577
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.220370182
Short name T250
Test name
Test status
Simulation time 1764496442 ps
CPU time 13.26 seconds
Started May 07 01:25:08 PM PDT 24
Finished May 07 01:25:23 PM PDT 24
Peak memory 237740 kb
Host smart-f9168433-593a-42b0-ad47-6cc0a84b1e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220370182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.220370182
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3583444630
Short name T229
Test name
Test status
Simulation time 2991869987 ps
CPU time 37.02 seconds
Started May 07 01:24:55 PM PDT 24
Finished May 07 01:25:33 PM PDT 24
Peak memory 221360 kb
Host smart-5383b73e-5f36-4568-812e-ad6845c2fd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583444630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3583444630
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3574401589
Short name T295
Test name
Test status
Simulation time 28393003454 ps
CPU time 23.04 seconds
Started May 07 01:23:29 PM PDT 24
Finished May 07 01:23:53 PM PDT 24
Peak memory 218700 kb
Host smart-abb93759-1363-46b4-ae70-834755085a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574401589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3574401589
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2958453454
Short name T70
Test name
Test status
Simulation time 141235719246 ps
CPU time 52.67 seconds
Started May 07 01:25:17 PM PDT 24
Finished May 07 01:26:11 PM PDT 24
Peak memory 238668 kb
Host smart-29720d58-a468-4751-ae48-e5483c2c4707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958453454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2958453454
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1624519924
Short name T376
Test name
Test status
Simulation time 42418770 ps
CPU time 0.75 seconds
Started May 07 01:15:38 PM PDT 24
Finished May 07 01:15:40 PM PDT 24
Peak memory 203880 kb
Host smart-8caf4840-0b82-4e8f-a1c2-eb178cae5f78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624519924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1624519924
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/default/19.spi_device_upload.3648979312
Short name T365
Test name
Test status
Simulation time 1498812493 ps
CPU time 8.53 seconds
Started May 07 01:23:56 PM PDT 24
Finished May 07 01:24:06 PM PDT 24
Peak memory 218664 kb
Host smart-ea8a0bb7-c564-411a-8587-17a3b8b2ad01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648979312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3648979312
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3103937715
Short name T298
Test name
Test status
Simulation time 3043383459 ps
CPU time 46.57 seconds
Started May 07 01:24:02 PM PDT 24
Finished May 07 01:24:51 PM PDT 24
Peak memory 224336 kb
Host smart-21e7564b-0b35-44ab-bc5f-c539ffa8ad76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103937715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3103937715
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.357167315
Short name T194
Test name
Test status
Simulation time 11111921699 ps
CPU time 11.95 seconds
Started May 07 01:23:54 PM PDT 24
Finished May 07 01:24:08 PM PDT 24
Peak memory 223420 kb
Host smart-7f409c92-2b1b-42b2-b8d6-ef9723200871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357167315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.357167315
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3615834003
Short name T225
Test name
Test status
Simulation time 3396270753 ps
CPU time 8.87 seconds
Started May 07 01:24:23 PM PDT 24
Finished May 07 01:24:34 PM PDT 24
Peak memory 222824 kb
Host smart-be8fee72-5e31-4b70-a2e5-9d2c02559a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615834003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3615834003
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3989712552
Short name T211
Test name
Test status
Simulation time 389351297 ps
CPU time 5.91 seconds
Started May 07 01:23:54 PM PDT 24
Finished May 07 01:24:02 PM PDT 24
Peak memory 223380 kb
Host smart-a88ae975-3b0e-421e-85c7-5852311249a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989712552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3989712552
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1234844665
Short name T293
Test name
Test status
Simulation time 8016441881 ps
CPU time 13.94 seconds
Started May 07 01:24:20 PM PDT 24
Finished May 07 01:24:35 PM PDT 24
Peak memory 239036 kb
Host smart-a34e66be-f949-4074-8107-8d6ae65d91cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234844665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1234844665
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2060843130
Short name T56
Test name
Test status
Simulation time 34505153262 ps
CPU time 34.26 seconds
Started May 07 01:23:30 PM PDT 24
Finished May 07 01:24:05 PM PDT 24
Peak memory 216176 kb
Host smart-9baaa411-4773-485c-9726-fb8ad0654b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060843130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2060843130
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3141259752
Short name T361
Test name
Test status
Simulation time 24564927130 ps
CPU time 61.38 seconds
Started May 07 01:23:12 PM PDT 24
Finished May 07 01:24:15 PM PDT 24
Peak memory 223108 kb
Host smart-6b215a7c-877b-4dac-8c45-81c6e8f078cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141259752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3141259752
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1827711146
Short name T290
Test name
Test status
Simulation time 11274490283 ps
CPU time 13.24 seconds
Started May 07 01:24:42 PM PDT 24
Finished May 07 01:24:57 PM PDT 24
Peak memory 218588 kb
Host smart-79b4d085-5996-433b-953a-83ac1dcf3437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827711146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1827711146
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1943572936
Short name T228
Test name
Test status
Simulation time 608249750 ps
CPU time 8.83 seconds
Started May 07 01:23:49 PM PDT 24
Finished May 07 01:24:01 PM PDT 24
Peak memory 226840 kb
Host smart-66bbd378-cba9-4528-9da5-4337574e4cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943572936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1943572936
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_intercept.2579247508
Short name T212
Test name
Test status
Simulation time 1696378050 ps
CPU time 5.01 seconds
Started May 07 01:24:56 PM PDT 24
Finished May 07 01:25:02 PM PDT 24
Peak memory 222600 kb
Host smart-ebb03a97-03fb-4b62-9e6a-94cf85f5a0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579247508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2579247508
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.2178155630
Short name T423
Test name
Test status
Simulation time 75078681 ps
CPU time 0.73 seconds
Started May 07 01:24:06 PM PDT 24
Finished May 07 01:24:09 PM PDT 24
Peak memory 205324 kb
Host smart-62964f52-5988-4241-9078-4d9f612de575
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178155630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
2178155630
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.4175188438
Short name T370
Test name
Test status
Simulation time 4522835078 ps
CPU time 55.04 seconds
Started May 07 01:23:10 PM PDT 24
Finished May 07 01:24:07 PM PDT 24
Peak memory 232564 kb
Host smart-4981da24-33bf-42f4-b6dd-436a7082f202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175188438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.4175188438
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.2210824577
Short name T726
Test name
Test status
Simulation time 8122154748 ps
CPU time 50.14 seconds
Started May 07 01:24:09 PM PDT 24
Finished May 07 01:25:02 PM PDT 24
Peak memory 216172 kb
Host smart-ccef153e-55ff-45ff-a125-33dbd4f24366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210824577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2210824577
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2491061228
Short name T175
Test name
Test status
Simulation time 858486419 ps
CPU time 5.05 seconds
Started May 07 01:24:22 PM PDT 24
Finished May 07 01:24:29 PM PDT 24
Peak memory 222364 kb
Host smart-0ea47e68-3812-4d69-b9d7-5a938cfc3e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491061228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2491061228
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_upload.2044682954
Short name T217
Test name
Test status
Simulation time 16194239552 ps
CPU time 13.12 seconds
Started May 07 01:24:47 PM PDT 24
Finished May 07 01:25:02 PM PDT 24
Peak memory 218544 kb
Host smart-ae7da69c-455b-4dfe-a573-719c2f903238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044682954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2044682954
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_intercept.763210214
Short name T364
Test name
Test status
Simulation time 619890424 ps
CPU time 9.63 seconds
Started May 07 01:23:47 PM PDT 24
Finished May 07 01:23:59 PM PDT 24
Peak memory 218436 kb
Host smart-c90080aa-1f69-40e3-8612-aa67dbffa53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763210214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.763210214
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1355699246
Short name T283
Test name
Test status
Simulation time 57157426251 ps
CPU time 96.77 seconds
Started May 07 01:23:19 PM PDT 24
Finished May 07 01:24:58 PM PDT 24
Peak memory 239564 kb
Host smart-f834ac43-6d16-4dae-a7e4-b508b4c5cccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355699246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1355699246
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_upload.489751874
Short name T180
Test name
Test status
Simulation time 571025819 ps
CPU time 5.02 seconds
Started May 07 01:23:23 PM PDT 24
Finished May 07 01:23:29 PM PDT 24
Peak memory 223120 kb
Host smart-2d0f75a7-8891-4330-a244-c38d41d13e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489751874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.489751874
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1065279616
Short name T65
Test name
Test status
Simulation time 2796183244 ps
CPU time 7.19 seconds
Started May 07 01:24:22 PM PDT 24
Finished May 07 01:24:31 PM PDT 24
Peak memory 220312 kb
Host smart-c31cc64d-661b-47ce-b1fc-f214a14ea770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065279616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1065279616
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3314229402
Short name T79
Test name
Test status
Simulation time 1217723370 ps
CPU time 4.7 seconds
Started May 07 01:24:51 PM PDT 24
Finished May 07 01:24:57 PM PDT 24
Peak memory 218204 kb
Host smart-290520cf-ecfe-4f6f-97cc-d37be94e1da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314229402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3314229402
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3302564316
Short name T359
Test name
Test status
Simulation time 7242565574 ps
CPU time 22.43 seconds
Started May 07 01:25:05 PM PDT 24
Finished May 07 01:25:29 PM PDT 24
Peak memory 218320 kb
Host smart-db1494d4-2e0f-49b0-acf9-bfbef6d3751e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302564316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3302564316
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3569141586
Short name T163
Test name
Test status
Simulation time 3517017662 ps
CPU time 21.85 seconds
Started May 07 01:15:26 PM PDT 24
Finished May 07 01:15:48 PM PDT 24
Peak memory 215852 kb
Host smart-1de8c167-a9de-4acb-a3e6-f6a10ba2070c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569141586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3569141586
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2698772698
Short name T63
Test name
Test status
Simulation time 15863467786 ps
CPU time 19.58 seconds
Started May 07 01:24:10 PM PDT 24
Finished May 07 01:24:32 PM PDT 24
Peak memory 235340 kb
Host smart-dadf9646-8acb-459d-8307-98cf7bdebff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698772698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2698772698
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2471054103
Short name T76
Test name
Test status
Simulation time 8545502210 ps
CPU time 23.32 seconds
Started May 07 01:24:18 PM PDT 24
Finished May 07 01:24:43 PM PDT 24
Peak memory 218344 kb
Host smart-f99579a8-9244-4d93-a624-8b0fbc6f85a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471054103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2471054103
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.83721541
Short name T387
Test name
Test status
Simulation time 28390141297 ps
CPU time 36.48 seconds
Started May 07 01:24:25 PM PDT 24
Finished May 07 01:25:03 PM PDT 24
Peak memory 216188 kb
Host smart-e0902509-cbbd-4d47-96d7-db93c9979308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83721541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.83721541
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.915796204
Short name T251
Test name
Test status
Simulation time 85084879 ps
CPU time 3.2 seconds
Started May 07 01:24:30 PM PDT 24
Finished May 07 01:24:35 PM PDT 24
Peak memory 222876 kb
Host smart-de43180d-5c2d-4f8d-bb79-99d9573839cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915796204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.915796204
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3912131204
Short name T199
Test name
Test status
Simulation time 3383191943 ps
CPU time 10.47 seconds
Started May 07 01:24:52 PM PDT 24
Finished May 07 01:25:03 PM PDT 24
Peak memory 222396 kb
Host smart-d294b740-5fde-474c-8883-a8a130d2b8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912131204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3912131204
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1843576970
Short name T245
Test name
Test status
Simulation time 18411560091 ps
CPU time 22.54 seconds
Started May 07 01:24:58 PM PDT 24
Finished May 07 01:25:22 PM PDT 24
Peak memory 222964 kb
Host smart-45323fcc-9056-4daa-b690-9e48462e9ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843576970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1843576970
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_intercept.3083490592
Short name T224
Test name
Test status
Simulation time 20923504168 ps
CPU time 21.78 seconds
Started May 07 01:23:35 PM PDT 24
Finished May 07 01:23:58 PM PDT 24
Peak memory 231964 kb
Host smart-89b4dc07-f6a1-4a43-9f1a-dffb4975ca6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083490592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3083490592
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.4172233389
Short name T155
Test name
Test status
Simulation time 1052335487 ps
CPU time 7.46 seconds
Started May 07 01:23:40 PM PDT 24
Finished May 07 01:23:49 PM PDT 24
Peak memory 232836 kb
Host smart-ee48c186-2f29-4452-b97d-7d91073850be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172233389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.4172233389
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3994328616
Short name T82
Test name
Test status
Simulation time 19464890953 ps
CPU time 47.73 seconds
Started May 07 01:24:23 PM PDT 24
Finished May 07 01:25:12 PM PDT 24
Peak memory 223916 kb
Host smart-adf774c5-9a28-4bbd-a30e-47baf1547d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994328616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3994328616
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1321275020
Short name T102
Test name
Test status
Simulation time 8120188121 ps
CPU time 16.33 seconds
Started May 07 01:24:43 PM PDT 24
Finished May 07 01:25:01 PM PDT 24
Peak memory 216180 kb
Host smart-0e3b6e7e-ad6e-46ba-b2d1-870a96f0b26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321275020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1321275020
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1444444420
Short name T90
Test name
Test status
Simulation time 125101199 ps
CPU time 2.73 seconds
Started May 07 01:23:07 PM PDT 24
Finished May 07 01:23:11 PM PDT 24
Peak memory 222560 kb
Host smart-cfd2125f-7057-4dad-931e-63d9421c0f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444444420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1444444420
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1184247327
Short name T594
Test name
Test status
Simulation time 4107326932 ps
CPU time 10.59 seconds
Started May 07 01:23:01 PM PDT 24
Finished May 07 01:23:13 PM PDT 24
Peak memory 232512 kb
Host smart-01fde31e-ac1c-40bd-ab17-adba69582820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184247327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1184247327
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.635211712
Short name T205
Test name
Test status
Simulation time 51112367935 ps
CPU time 96.79 seconds
Started May 07 01:23:38 PM PDT 24
Finished May 07 01:25:16 PM PDT 24
Peak memory 218980 kb
Host smart-cf330b17-c622-42f8-90e6-6f25d4adce1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635211712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.635211712
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3229732697
Short name T275
Test name
Test status
Simulation time 36112274454 ps
CPU time 25.07 seconds
Started May 07 01:23:48 PM PDT 24
Finished May 07 01:24:15 PM PDT 24
Peak memory 235524 kb
Host smart-cb7ba186-303c-4ae0-a76e-7de2b1236fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229732697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3229732697
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_upload.998129944
Short name T383
Test name
Test status
Simulation time 1075964174 ps
CPU time 5.49 seconds
Started May 07 01:23:56 PM PDT 24
Finished May 07 01:24:03 PM PDT 24
Peak memory 232112 kb
Host smart-c65e3975-5405-48f1-8234-4a4e04648337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998129944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.998129944
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1033801924
Short name T64
Test name
Test status
Simulation time 24586578594 ps
CPU time 16.83 seconds
Started May 07 01:23:58 PM PDT 24
Finished May 07 01:24:17 PM PDT 24
Peak memory 223496 kb
Host smart-92233328-f92a-49e8-bd5d-b11ef50b73d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033801924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1033801924
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1580309319
Short name T197
Test name
Test status
Simulation time 914583404 ps
CPU time 5.08 seconds
Started May 07 01:23:42 PM PDT 24
Finished May 07 01:23:48 PM PDT 24
Peak memory 223532 kb
Host smart-96b86278-c2f3-4b4f-9ae2-acbd4360f5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580309319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1580309319
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.4056891009
Short name T289
Test name
Test status
Simulation time 1173922555 ps
CPU time 7.61 seconds
Started May 07 01:23:50 PM PDT 24
Finished May 07 01:24:00 PM PDT 24
Peak memory 216388 kb
Host smart-524774f5-c4a5-45b0-acd1-64d29dc1b4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056891009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.4056891009
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.708296388
Short name T351
Test name
Test status
Simulation time 691240430 ps
CPU time 2.1 seconds
Started May 07 01:23:54 PM PDT 24
Finished May 07 01:23:58 PM PDT 24
Peak memory 218412 kb
Host smart-4cccc93c-1c2d-4121-a426-d5b420e5d08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708296388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.708296388
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.916766468
Short name T241
Test name
Test status
Simulation time 18611169475 ps
CPU time 48.85 seconds
Started May 07 01:23:17 PM PDT 24
Finished May 07 01:24:07 PM PDT 24
Peak memory 227400 kb
Host smart-bf902608-6e4e-40c9-b6a5-fefaae190855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916766468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
916766468
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1326732225
Short name T299
Test name
Test status
Simulation time 968785170 ps
CPU time 17.53 seconds
Started May 07 01:23:53 PM PDT 24
Finished May 07 01:24:13 PM PDT 24
Peak memory 236444 kb
Host smart-811261de-53a4-4702-bd99-ee1aec3aaf1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326732225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1326732225
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1837496473
Short name T255
Test name
Test status
Simulation time 12215138626 ps
CPU time 20.96 seconds
Started May 07 01:24:10 PM PDT 24
Finished May 07 01:24:34 PM PDT 24
Peak memory 223376 kb
Host smart-de53e2fc-f655-441a-a55b-396373310d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837496473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1837496473
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1948630931
Short name T233
Test name
Test status
Simulation time 2507260204 ps
CPU time 5.47 seconds
Started May 07 01:24:04 PM PDT 24
Finished May 07 01:24:12 PM PDT 24
Peak memory 221208 kb
Host smart-031b3919-8152-48d4-8725-7872064095fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948630931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1948630931
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3034836566
Short name T344
Test name
Test status
Simulation time 372554645 ps
CPU time 6.4 seconds
Started May 07 01:23:54 PM PDT 24
Finished May 07 01:24:08 PM PDT 24
Peak memory 222972 kb
Host smart-3910d3d9-a884-423b-9957-61cd497b75a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034836566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3034836566
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3423220145
Short name T296
Test name
Test status
Simulation time 12192456651 ps
CPU time 90.08 seconds
Started May 07 01:24:12 PM PDT 24
Finished May 07 01:25:45 PM PDT 24
Peak memory 240352 kb
Host smart-008b80dc-37b9-43bb-a2d4-aac80b30c194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423220145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3423220145
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_upload.2089848624
Short name T46
Test name
Test status
Simulation time 13010907485 ps
CPU time 10.19 seconds
Started May 07 01:24:27 PM PDT 24
Finished May 07 01:24:39 PM PDT 24
Peak memory 218656 kb
Host smart-77725fb2-b0cf-466a-8bee-0213bd4a4dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089848624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2089848624
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.980026203
Short name T209
Test name
Test status
Simulation time 309631044 ps
CPU time 5.67 seconds
Started May 07 01:24:23 PM PDT 24
Finished May 07 01:24:31 PM PDT 24
Peak memory 239236 kb
Host smart-ace8c1d4-d7ab-402e-b12d-eeef440c6307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980026203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.980026203
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2313708227
Short name T238
Test name
Test status
Simulation time 125437756 ps
CPU time 2.38 seconds
Started May 07 01:24:45 PM PDT 24
Finished May 07 01:24:49 PM PDT 24
Peak memory 221268 kb
Host smart-2d2ed07c-093b-43d5-a0b2-dacb86d37e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313708227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2313708227
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1824154738
Short name T292
Test name
Test status
Simulation time 584172022 ps
CPU time 7.43 seconds
Started May 07 01:24:43 PM PDT 24
Finished May 07 01:24:52 PM PDT 24
Peak memory 224240 kb
Host smart-1ebafc0d-68b2-495c-a1d9-f474ee61aa4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824154738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1824154738
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2747358951
Short name T276
Test name
Test status
Simulation time 60719852 ps
CPU time 2.38 seconds
Started May 07 01:24:43 PM PDT 24
Finished May 07 01:24:47 PM PDT 24
Peak memory 221564 kb
Host smart-0831b812-a3ab-42a1-b251-fcc6c9faec23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747358951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2747358951
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_upload.2912581765
Short name T181
Test name
Test status
Simulation time 509092041 ps
CPU time 2.39 seconds
Started May 07 01:24:53 PM PDT 24
Finished May 07 01:24:56 PM PDT 24
Peak memory 216044 kb
Host smart-2cfd71b7-992c-4f7f-b736-d453e5c46e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912581765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2912581765
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_intercept.452540012
Short name T191
Test name
Test status
Simulation time 85210531 ps
CPU time 3.31 seconds
Started May 07 01:25:00 PM PDT 24
Finished May 07 01:25:05 PM PDT 24
Peak memory 222684 kb
Host smart-5310e1a8-ad0e-4d68-a2b4-a09e578eb7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452540012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.452540012
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_intercept.24163516
Short name T317
Test name
Test status
Simulation time 570719078 ps
CPU time 5.32 seconds
Started May 07 01:25:18 PM PDT 24
Finished May 07 01:25:26 PM PDT 24
Peak memory 224164 kb
Host smart-4b7a7708-56b0-4c51-8916-6f19300d8eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24163516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.24163516
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.4196668341
Short name T75
Test name
Test status
Simulation time 2414599650 ps
CPU time 15.26 seconds
Started May 07 01:23:45 PM PDT 24
Finished May 07 01:24:01 PM PDT 24
Peak memory 232488 kb
Host smart-94562595-2d79-4e39-a7db-5e39181b655b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196668341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.4196668341
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.836895769
Short name T282
Test name
Test status
Simulation time 13160802755 ps
CPU time 16.72 seconds
Started May 07 01:23:47 PM PDT 24
Finished May 07 01:24:06 PM PDT 24
Peak memory 220848 kb
Host smart-88e266cd-619e-4788-a3e0-1ebc508889c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836895769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.836895769
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2018046589
Short name T265
Test name
Test status
Simulation time 81806064 ps
CPU time 2.31 seconds
Started May 07 01:23:40 PM PDT 24
Finished May 07 01:23:44 PM PDT 24
Peak memory 222168 kb
Host smart-cb8fb0cb-90f6-41c4-85ad-b962cd0c93ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018046589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2018046589
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3703255693
Short name T107
Test name
Test status
Simulation time 6686444528 ps
CPU time 93.24 seconds
Started May 07 01:24:11 PM PDT 24
Finished May 07 01:25:47 PM PDT 24
Peak memory 248936 kb
Host smart-c5415b8f-4937-4e0d-a96e-ee41f9f52b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703255693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3703255693
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1898635369
Short name T122
Test name
Test status
Simulation time 60286082 ps
CPU time 3.8 seconds
Started May 07 01:15:01 PM PDT 24
Finished May 07 01:15:06 PM PDT 24
Peak memory 216652 kb
Host smart-8356fe7f-0c7e-4652-ab6d-fb054ee607fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898635369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
898635369
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.667801074
Short name T382
Test name
Test status
Simulation time 1079972884 ps
CPU time 13.72 seconds
Started May 07 01:14:45 PM PDT 24
Finished May 07 01:14:59 PM PDT 24
Peak memory 215668 kb
Host smart-6eceb7b3-fba7-460f-b88d-31aea1939e3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667801074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_
tl_intg_err.667801074
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2693663901
Short name T379
Test name
Test status
Simulation time 771311196 ps
CPU time 13.2 seconds
Started May 07 01:15:21 PM PDT 24
Finished May 07 01:15:35 PM PDT 24
Peak memory 215588 kb
Host smart-98971ebd-bf0d-405a-86bd-2b0944193f82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693663901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2693663901
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.618415239
Short name T752
Test name
Test status
Simulation time 34412323 ps
CPU time 0.76 seconds
Started May 07 01:15:29 PM PDT 24
Finished May 07 01:15:31 PM PDT 24
Peak memory 203916 kb
Host smart-2c7a31e5-7ef7-4f7f-b1f6-cf235816b5ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618415239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.618415239
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3989687477
Short name T322
Test name
Test status
Simulation time 1873413709 ps
CPU time 10.48 seconds
Started May 07 01:23:17 PM PDT 24
Finished May 07 01:23:28 PM PDT 24
Peak memory 222724 kb
Host smart-66870aa7-2f6b-4eba-ac8d-230a6f77e641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989687477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3989687477
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_intercept.620185650
Short name T340
Test name
Test status
Simulation time 5241225292 ps
CPU time 28.98 seconds
Started May 07 01:23:14 PM PDT 24
Finished May 07 01:23:44 PM PDT 24
Peak memory 222456 kb
Host smart-a138ce65-3487-43ae-bf23-c3d53ceb45d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620185650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.620185650
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1542394887
Short name T67
Test name
Test status
Simulation time 16249565721 ps
CPU time 9.36 seconds
Started May 07 01:23:17 PM PDT 24
Finished May 07 01:23:27 PM PDT 24
Peak memory 220084 kb
Host smart-fc5cb01b-5c43-4707-afcf-3cddb13058cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542394887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1542394887
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1896828751
Short name T443
Test name
Test status
Simulation time 56148143 ps
CPU time 0.86 seconds
Started May 07 01:22:59 PM PDT 24
Finished May 07 01:23:01 PM PDT 24
Peak memory 205504 kb
Host smart-db011108-458a-4048-9c8d-02b0a09fbe52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896828751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1896828751
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2495665791
Short name T220
Test name
Test status
Simulation time 4699255946 ps
CPU time 7.68 seconds
Started May 07 01:23:45 PM PDT 24
Finished May 07 01:23:54 PM PDT 24
Peak memory 235980 kb
Host smart-6d5aadf6-b00f-47fb-ab18-cbd6f4c57b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495665791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2495665791
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_upload.1696592075
Short name T216
Test name
Test status
Simulation time 555007336 ps
CPU time 4.12 seconds
Started May 07 01:23:57 PM PDT 24
Finished May 07 01:24:03 PM PDT 24
Peak memory 222308 kb
Host smart-eea9df27-9443-4ee8-bc59-bdbe58d9f179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696592075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1696592075
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1657274382
Short name T316
Test name
Test status
Simulation time 7291409914 ps
CPU time 14.36 seconds
Started May 07 01:23:48 PM PDT 24
Finished May 07 01:24:04 PM PDT 24
Peak memory 218464 kb
Host smart-6aba248e-9fb7-43f8-a7a1-c25618dcb668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657274382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1657274382
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.410721573
Short name T256
Test name
Test status
Simulation time 49338647 ps
CPU time 2.29 seconds
Started May 07 01:23:58 PM PDT 24
Finished May 07 01:24:02 PM PDT 24
Peak memory 222760 kb
Host smart-87995607-6ec8-45e3-a551-b411a8a6c416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410721573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.410721573
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_upload.2483033773
Short name T226
Test name
Test status
Simulation time 1384619150 ps
CPU time 3.96 seconds
Started May 07 01:23:47 PM PDT 24
Finished May 07 01:23:52 PM PDT 24
Peak memory 218432 kb
Host smart-c756a6d4-7b70-4b8f-ab19-e1405afe93ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483033773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2483033773
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.929920114
Short name T279
Test name
Test status
Simulation time 4415954620 ps
CPU time 14.04 seconds
Started May 07 01:23:49 PM PDT 24
Finished May 07 01:24:06 PM PDT 24
Peak memory 218652 kb
Host smart-20ebc401-3701-4fba-a635-64ad50b0fddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929920114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap
.929920114
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1758414317
Short name T247
Test name
Test status
Simulation time 2423882661 ps
CPU time 4.5 seconds
Started May 07 01:23:47 PM PDT 24
Finished May 07 01:23:52 PM PDT 24
Peak memory 216496 kb
Host smart-f3f013e2-cdad-4c0a-8fce-d2f46df44403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758414317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1758414317
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3066132101
Short name T27
Test name
Test status
Simulation time 2187826983 ps
CPU time 7.34 seconds
Started May 07 01:24:00 PM PDT 24
Finished May 07 01:24:10 PM PDT 24
Peak memory 223040 kb
Host smart-8911b505-5921-4b22-8621-56e52992b9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066132101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3066132101
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_upload.736268057
Short name T235
Test name
Test status
Simulation time 979537319 ps
CPU time 6 seconds
Started May 07 01:24:00 PM PDT 24
Finished May 07 01:24:07 PM PDT 24
Peak memory 216068 kb
Host smart-2edc0c4a-9d0c-46d2-a185-7759ce7ee971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736268057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.736268057
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.822009051
Short name T353
Test name
Test status
Simulation time 53214007 ps
CPU time 2.26 seconds
Started May 07 01:23:53 PM PDT 24
Finished May 07 01:23:58 PM PDT 24
Peak memory 218316 kb
Host smart-b4925aa8-a341-4604-abf7-df052ae091e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822009051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.822009051
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1288711860
Short name T335
Test name
Test status
Simulation time 8698543132 ps
CPU time 46.76 seconds
Started May 07 01:24:00 PM PDT 24
Finished May 07 01:24:49 PM PDT 24
Peak memory 233208 kb
Host smart-fa8dafd9-eebe-44f0-bb1f-65df40526e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288711860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1288711860
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3990886556
Short name T349
Test name
Test status
Simulation time 682706959 ps
CPU time 11.21 seconds
Started May 07 01:24:08 PM PDT 24
Finished May 07 01:24:22 PM PDT 24
Peak memory 231996 kb
Host smart-be5b9cde-0f4a-43ed-a88b-bd733e3a29c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990886556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3990886556
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1473021615
Short name T195
Test name
Test status
Simulation time 3023964840 ps
CPU time 8.3 seconds
Started May 07 01:23:53 PM PDT 24
Finished May 07 01:24:04 PM PDT 24
Peak memory 221852 kb
Host smart-398d8585-437a-4e4c-ad43-8fbce7734998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473021615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1473021615
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1913739561
Short name T272
Test name
Test status
Simulation time 2215285660 ps
CPU time 3.71 seconds
Started May 07 01:24:16 PM PDT 24
Finished May 07 01:24:22 PM PDT 24
Peak memory 219808 kb
Host smart-e26750a4-8a1a-4990-bb69-126bc2d2e859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913739561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1913739561
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2865876475
Short name T268
Test name
Test status
Simulation time 10102198581 ps
CPU time 20.58 seconds
Started May 07 01:24:31 PM PDT 24
Finished May 07 01:24:53 PM PDT 24
Peak memory 234628 kb
Host smart-1526e44c-c1eb-4ed3-95aa-258c993a8df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865876475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2865876475
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.4022299596
Short name T106
Test name
Test status
Simulation time 384256709 ps
CPU time 9.65 seconds
Started May 07 01:24:26 PM PDT 24
Finished May 07 01:24:37 PM PDT 24
Peak memory 240688 kb
Host smart-73c0d451-d81b-4896-8c5f-253ba11bd37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022299596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.4022299596
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3449099298
Short name T261
Test name
Test status
Simulation time 6848188985 ps
CPU time 18.14 seconds
Started May 07 01:24:23 PM PDT 24
Finished May 07 01:24:43 PM PDT 24
Peak memory 232908 kb
Host smart-04ec91e8-3f41-400e-a8cf-6acdb65fcab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449099298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3449099298
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3328092157
Short name T222
Test name
Test status
Simulation time 3033336477 ps
CPU time 6.48 seconds
Started May 07 01:24:28 PM PDT 24
Finished May 07 01:24:36 PM PDT 24
Peak memory 222084 kb
Host smart-9bf4c458-f58a-451f-b2e8-ea4898150a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328092157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3328092157
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2691874482
Short name T183
Test name
Test status
Simulation time 670840787 ps
CPU time 9.66 seconds
Started May 07 01:24:20 PM PDT 24
Finished May 07 01:24:31 PM PDT 24
Peak memory 234280 kb
Host smart-bb3dc394-792e-4820-9e19-07690a9945e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691874482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2691874482
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2120508030
Short name T227
Test name
Test status
Simulation time 11108934191 ps
CPU time 12.72 seconds
Started May 07 01:24:23 PM PDT 24
Finished May 07 01:24:37 PM PDT 24
Peak memory 234256 kb
Host smart-c5a09c75-9429-4cf8-aeb1-2d35f51a6c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120508030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2120508030
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_intercept.910914130
Short name T318
Test name
Test status
Simulation time 2570463455 ps
CPU time 23.4 seconds
Started May 07 01:24:31 PM PDT 24
Finished May 07 01:24:56 PM PDT 24
Peak memory 222632 kb
Host smart-fe62b44b-c1f0-4490-ae70-4c186602d3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910914130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.910914130
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2085752655
Short name T48
Test name
Test status
Simulation time 642511498 ps
CPU time 8.72 seconds
Started May 07 01:24:39 PM PDT 24
Finished May 07 01:24:48 PM PDT 24
Peak memory 224292 kb
Host smart-fe2a1339-071d-45ff-a6b1-18da16e69954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085752655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2085752655
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1423080291
Short name T193
Test name
Test status
Simulation time 299234858 ps
CPU time 5 seconds
Started May 07 01:24:46 PM PDT 24
Finished May 07 01:24:53 PM PDT 24
Peak memory 218364 kb
Host smart-1d3b935d-09ea-400f-b9a3-62cb3b6af89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423080291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1423080291
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2702459646
Short name T307
Test name
Test status
Simulation time 2380353956 ps
CPU time 41.32 seconds
Started May 07 01:24:41 PM PDT 24
Finished May 07 01:25:23 PM PDT 24
Peak memory 240744 kb
Host smart-a910f482-78e4-4771-b6f5-0074f684c256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702459646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2702459646
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2398953694
Short name T348
Test name
Test status
Simulation time 295314449 ps
CPU time 4.18 seconds
Started May 07 01:24:40 PM PDT 24
Finished May 07 01:24:45 PM PDT 24
Peak memory 223244 kb
Host smart-2222d591-99db-477c-af3b-7c9d5bf74cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398953694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2398953694
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3886241253
Short name T287
Test name
Test status
Simulation time 56242505787 ps
CPU time 32.75 seconds
Started May 07 01:24:52 PM PDT 24
Finished May 07 01:25:25 PM PDT 24
Peak memory 220820 kb
Host smart-057049c2-01aa-4a58-a096-b420018a7435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886241253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3886241253
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3427202408
Short name T352
Test name
Test status
Simulation time 1667214582 ps
CPU time 7.21 seconds
Started May 07 01:24:33 PM PDT 24
Finished May 07 01:24:41 PM PDT 24
Peak memory 222888 kb
Host smart-c1855c0b-f0bf-4367-945c-4d494dd8476a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427202408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3427202408
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.212961536
Short name T230
Test name
Test status
Simulation time 176845491 ps
CPU time 2.91 seconds
Started May 07 01:24:56 PM PDT 24
Finished May 07 01:25:00 PM PDT 24
Peak memory 216352 kb
Host smart-ea795ff3-b46d-4efc-ad4f-6a1c4317d16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212961536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.212961536
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1105685418
Short name T253
Test name
Test status
Simulation time 3704388775 ps
CPU time 25.99 seconds
Started May 07 01:23:32 PM PDT 24
Finished May 07 01:24:00 PM PDT 24
Peak memory 218880 kb
Host smart-a9901945-5019-41f4-9581-29c680285900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105685418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1105685418
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1175771809
Short name T264
Test name
Test status
Simulation time 12212847049 ps
CPU time 37.83 seconds
Started May 07 01:24:55 PM PDT 24
Finished May 07 01:25:34 PM PDT 24
Peak memory 238148 kb
Host smart-a4126f1f-e72a-4c29-a7f3-d6c9d602ac44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175771809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1175771809
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.577643903
Short name T300
Test name
Test status
Simulation time 6360080407 ps
CPU time 26 seconds
Started May 07 01:25:18 PM PDT 24
Finished May 07 01:25:46 PM PDT 24
Peak memory 232248 kb
Host smart-b911166d-b48e-4d22-9b52-00372e17b6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577643903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.577643903
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3528135920
Short name T200
Test name
Test status
Simulation time 252006169 ps
CPU time 3.63 seconds
Started May 07 01:25:18 PM PDT 24
Finished May 07 01:25:23 PM PDT 24
Peak memory 222360 kb
Host smart-037e536f-463b-48c3-8fc0-2acbc7438a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528135920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3528135920
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_upload.2148320521
Short name T346
Test name
Test status
Simulation time 11508440316 ps
CPU time 25.51 seconds
Started May 07 01:25:15 PM PDT 24
Finished May 07 01:25:42 PM PDT 24
Peak memory 239628 kb
Host smart-a4f75ee3-cf2f-4fec-b389-51bbfbd36154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148320521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2148320521
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2315907406
Short name T206
Test name
Test status
Simulation time 2826535379 ps
CPU time 10.19 seconds
Started May 07 01:25:10 PM PDT 24
Finished May 07 01:25:21 PM PDT 24
Peak memory 218884 kb
Host smart-2e42ba2d-2324-4803-86d9-5fb1252bff2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315907406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2315907406
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1902942028
Short name T218
Test name
Test status
Simulation time 3693453372 ps
CPU time 13 seconds
Started May 07 01:23:22 PM PDT 24
Finished May 07 01:23:36 PM PDT 24
Peak memory 218564 kb
Host smart-b151b12e-da8a-457f-ab09-2e009232857b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902942028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.1902942028
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3607380430
Short name T431
Test name
Test status
Simulation time 26606525 ps
CPU time 0.8 seconds
Started May 07 01:23:36 PM PDT 24
Finished May 07 01:23:39 PM PDT 24
Peak memory 206096 kb
Host smart-b73a6494-4744-4296-84bf-c8690505468f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607380430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3607380430
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3117733799
Short name T93
Test name
Test status
Simulation time 70501373 ps
CPU time 1.04 seconds
Started May 07 01:14:54 PM PDT 24
Finished May 07 01:14:56 PM PDT 24
Peak memory 206924 kb
Host smart-389feb89-f46d-45cc-8029-90d938892ed3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117733799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3117733799
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3580239349
Short name T838
Test name
Test status
Simulation time 99396505 ps
CPU time 5.45 seconds
Started May 07 01:15:20 PM PDT 24
Finished May 07 01:15:26 PM PDT 24
Peak memory 215656 kb
Host smart-4e4759b8-7e73-4768-966a-a4ceae8dc8c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580239349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3580239349
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.1594556480
Short name T86
Test name
Test status
Simulation time 216416294 ps
CPU time 2.8 seconds
Started May 07 01:23:31 PM PDT 24
Finished May 07 01:23:35 PM PDT 24
Peak memory 223140 kb
Host smart-295bba6d-e60d-455a-933f-a49b64b5c4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594556480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1594556480
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1847077897
Short name T467
Test name
Test status
Simulation time 111671077 ps
CPU time 4.06 seconds
Started May 07 01:23:44 PM PDT 24
Finished May 07 01:23:49 PM PDT 24
Peak memory 222732 kb
Host smart-6ddfe9c8-8be6-4f8f-99f0-b4fa1798ed96
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1847077897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1847077897
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2357856421
Short name T130
Test name
Test status
Simulation time 633068727 ps
CPU time 7.23 seconds
Started May 07 01:14:48 PM PDT 24
Finished May 07 01:14:56 PM PDT 24
Peak memory 207300 kb
Host smart-531f963a-3220-4048-aa63-a1647d702e67
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357856421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2357856421
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3094559027
Short name T146
Test name
Test status
Simulation time 2188367330 ps
CPU time 23.34 seconds
Started May 07 01:14:46 PM PDT 24
Finished May 07 01:15:10 PM PDT 24
Peak memory 207156 kb
Host smart-0379cf52-8fde-4395-acac-f95fba265536
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094559027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3094559027
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1521361479
Short name T95
Test name
Test status
Simulation time 273585361 ps
CPU time 1.21 seconds
Started May 07 01:14:47 PM PDT 24
Finished May 07 01:14:49 PM PDT 24
Peak memory 207248 kb
Host smart-51c35cbb-355b-4146-bb1c-da1bcc8714ee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521361479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1521361479
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4200256164
Short name T805
Test name
Test status
Simulation time 211577763 ps
CPU time 1.74 seconds
Started May 07 01:14:47 PM PDT 24
Finished May 07 01:14:49 PM PDT 24
Peak memory 215716 kb
Host smart-712684f2-7df2-4ea1-bfa4-6e4bf6835e6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200256164 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.4200256164
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1606353949
Short name T828
Test name
Test status
Simulation time 59269315 ps
CPU time 1.97 seconds
Started May 07 01:14:45 PM PDT 24
Finished May 07 01:14:48 PM PDT 24
Peak memory 215540 kb
Host smart-1b6b81f9-dbb4-42bc-9432-f972e45eaaac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606353949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
606353949
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.899802623
Short name T744
Test name
Test status
Simulation time 27608373 ps
CPU time 0.68 seconds
Started May 07 01:14:47 PM PDT 24
Finished May 07 01:14:49 PM PDT 24
Peak memory 203656 kb
Host smart-608feb2e-4abb-4c77-bb28-b37da74f30ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899802623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.899802623
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3450441366
Short name T841
Test name
Test status
Simulation time 25381715 ps
CPU time 1.74 seconds
Started May 07 01:14:48 PM PDT 24
Finished May 07 01:14:50 PM PDT 24
Peak memory 215612 kb
Host smart-2c423ab8-6944-4ac5-94bd-5a6bb5fd714d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450441366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3450441366
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2154417699
Short name T837
Test name
Test status
Simulation time 11441555 ps
CPU time 0.68 seconds
Started May 07 01:14:49 PM PDT 24
Finished May 07 01:14:50 PM PDT 24
Peak memory 203632 kb
Host smart-a4f59b1e-0418-49bb-b377-56382319d80a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154417699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2154417699
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.285283898
Short name T811
Test name
Test status
Simulation time 423312185 ps
CPU time 4.47 seconds
Started May 07 01:14:48 PM PDT 24
Finished May 07 01:14:53 PM PDT 24
Peak memory 215568 kb
Host smart-fa443750-0b6c-4c1b-b5ad-0d969ad72013
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285283898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp
i_device_same_csr_outstanding.285283898
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.131216868
Short name T831
Test name
Test status
Simulation time 38804987 ps
CPU time 2.51 seconds
Started May 07 01:14:47 PM PDT 24
Finished May 07 01:14:50 PM PDT 24
Peak memory 215692 kb
Host smart-6c3fcb00-1091-4085-bcec-ea2beafd0026
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131216868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.131216868
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3086752738
Short name T139
Test name
Test status
Simulation time 3411854235 ps
CPU time 22.66 seconds
Started May 07 01:14:52 PM PDT 24
Finished May 07 01:15:16 PM PDT 24
Peak memory 215884 kb
Host smart-7c8e726a-e2eb-44eb-9956-ff80bd2c4c8d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086752738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3086752738
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.260158914
Short name T820
Test name
Test status
Simulation time 8581364249 ps
CPU time 37.78 seconds
Started May 07 01:14:52 PM PDT 24
Finished May 07 01:15:31 PM PDT 24
Peak memory 207308 kb
Host smart-2c0ad3a3-d26b-46a1-856b-1875d62ad4c0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260158914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.260158914
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3017425718
Short name T793
Test name
Test status
Simulation time 1711541587 ps
CPU time 3.75 seconds
Started May 07 01:14:52 PM PDT 24
Finished May 07 01:14:57 PM PDT 24
Peak memory 218300 kb
Host smart-c7ed5a38-029b-435c-b3b3-5573a5cb826e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017425718 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3017425718
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3871786577
Short name T759
Test name
Test status
Simulation time 32322402 ps
CPU time 1.3 seconds
Started May 07 01:14:53 PM PDT 24
Finished May 07 01:14:56 PM PDT 24
Peak memory 215512 kb
Host smart-c1bc4ca2-f4e3-4fca-8fc8-4b9bda630c4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871786577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
871786577
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.399768419
Short name T842
Test name
Test status
Simulation time 29667529 ps
CPU time 0.77 seconds
Started May 07 01:14:54 PM PDT 24
Finished May 07 01:14:55 PM PDT 24
Peak memory 203876 kb
Host smart-ccf83986-35b4-4f02-a784-d41df64e29f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399768419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.399768419
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.4239918982
Short name T136
Test name
Test status
Simulation time 113649963 ps
CPU time 2.11 seconds
Started May 07 01:15:00 PM PDT 24
Finished May 07 01:15:03 PM PDT 24
Peak memory 215696 kb
Host smart-1748a9a0-b867-40f8-8ed0-05152ad751c6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239918982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.4239918982
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4047164547
Short name T856
Test name
Test status
Simulation time 33112845 ps
CPU time 0.66 seconds
Started May 07 01:14:53 PM PDT 24
Finished May 07 01:14:55 PM PDT 24
Peak memory 203620 kb
Host smart-6438ffbd-d15b-4137-a433-9c47338ae59c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047164547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.4047164547
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1142944536
Short name T152
Test name
Test status
Simulation time 378644877 ps
CPU time 2.71 seconds
Started May 07 01:14:54 PM PDT 24
Finished May 07 01:14:58 PM PDT 24
Peak memory 215612 kb
Host smart-2a7aeb2c-ddc9-4246-93f6-2b4b9d5f6ebd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142944536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1142944536
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1727459090
Short name T126
Test name
Test status
Simulation time 32713475 ps
CPU time 2.02 seconds
Started May 07 01:14:54 PM PDT 24
Finished May 07 01:14:57 PM PDT 24
Peak memory 215708 kb
Host smart-03b63e46-e141-49e1-ada1-d15e10a1b9b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727459090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
727459090
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2788091489
Short name T786
Test name
Test status
Simulation time 1978486160 ps
CPU time 14.27 seconds
Started May 07 01:15:00 PM PDT 24
Finished May 07 01:15:15 PM PDT 24
Peak memory 215788 kb
Host smart-c534609b-1c85-4ef9-8d07-9ca6c988d590
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788091489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2788091489
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1663715088
Short name T761
Test name
Test status
Simulation time 46619937 ps
CPU time 3.23 seconds
Started May 07 01:15:19 PM PDT 24
Finished May 07 01:15:23 PM PDT 24
Peak memory 216728 kb
Host smart-af82c562-3445-460c-bf93-2371ebcd3011
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663715088 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1663715088
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.4182502378
Short name T143
Test name
Test status
Simulation time 38362139 ps
CPU time 2.45 seconds
Started May 07 01:15:20 PM PDT 24
Finished May 07 01:15:24 PM PDT 24
Peak memory 215508 kb
Host smart-3740bcda-adba-4313-9d37-ab9c96af7b73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182502378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
4182502378
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3100433447
Short name T851
Test name
Test status
Simulation time 28081410 ps
CPU time 0.74 seconds
Started May 07 01:15:19 PM PDT 24
Finished May 07 01:15:21 PM PDT 24
Peak memory 203568 kb
Host smart-be95ac54-3cd8-435e-b89e-ba37409721af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100433447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3100433447
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3788202577
Short name T41
Test name
Test status
Simulation time 229272527 ps
CPU time 3.66 seconds
Started May 07 01:15:18 PM PDT 24
Finished May 07 01:15:22 PM PDT 24
Peak memory 215628 kb
Host smart-8aa3970d-afed-4d7f-97df-b0d51d10ebfc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788202577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.3788202577
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3505107245
Short name T111
Test name
Test status
Simulation time 43918547 ps
CPU time 1.42 seconds
Started May 07 01:15:20 PM PDT 24
Finished May 07 01:15:23 PM PDT 24
Peak memory 215668 kb
Host smart-b2e9af3a-6a4d-4eb3-adb7-1c54dc45dafc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505107245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3505107245
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1614553950
Short name T774
Test name
Test status
Simulation time 1156171976 ps
CPU time 7.36 seconds
Started May 07 01:15:21 PM PDT 24
Finished May 07 01:15:29 PM PDT 24
Peak memory 215524 kb
Host smart-9509ac67-096a-4aa4-964c-f47dff037890
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614553950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1614553950
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3416207231
Short name T792
Test name
Test status
Simulation time 245885141 ps
CPU time 1.88 seconds
Started May 07 01:15:19 PM PDT 24
Finished May 07 01:15:22 PM PDT 24
Peak memory 216752 kb
Host smart-78a8cab4-9f4f-4c66-86a4-928194bb47e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416207231 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3416207231
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3698668358
Short name T745
Test name
Test status
Simulation time 18317372 ps
CPU time 0.75 seconds
Started May 07 01:15:22 PM PDT 24
Finished May 07 01:15:24 PM PDT 24
Peak memory 203652 kb
Host smart-ccc435f4-4b9e-405c-890f-12aeee0813c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698668358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3698668358
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.716850276
Short name T790
Test name
Test status
Simulation time 766941961 ps
CPU time 4.5 seconds
Started May 07 01:15:20 PM PDT 24
Finished May 07 01:15:25 PM PDT 24
Peak memory 215548 kb
Host smart-5809964a-735b-4053-9824-6b1c76c44612
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716850276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.s
pi_device_same_csr_outstanding.716850276
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.4238519880
Short name T816
Test name
Test status
Simulation time 3749184416 ps
CPU time 20.16 seconds
Started May 07 01:15:20 PM PDT 24
Finished May 07 01:15:42 PM PDT 24
Peak memory 215668 kb
Host smart-0ca0b796-4e4e-455b-807a-b58aff6e7569
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238519880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.4238519880
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2725588216
Short name T787
Test name
Test status
Simulation time 218638089 ps
CPU time 3.89 seconds
Started May 07 01:15:19 PM PDT 24
Finished May 07 01:15:24 PM PDT 24
Peak memory 218076 kb
Host smart-79cfe602-8d55-411c-bf46-eb0935886019
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725588216 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2725588216
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2377965135
Short name T148
Test name
Test status
Simulation time 66650068 ps
CPU time 1.12 seconds
Started May 07 01:15:20 PM PDT 24
Finished May 07 01:15:22 PM PDT 24
Peak memory 207292 kb
Host smart-829f9526-c039-47a0-908a-af002090a4bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377965135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2377965135
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2638244921
Short name T812
Test name
Test status
Simulation time 22232127 ps
CPU time 0.71 seconds
Started May 07 01:15:19 PM PDT 24
Finished May 07 01:15:21 PM PDT 24
Peak memory 203896 kb
Host smart-7c05a245-0935-47e7-b92a-0e5f1f613952
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638244921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2638244921
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1300553553
Short name T855
Test name
Test status
Simulation time 79715660 ps
CPU time 2.46 seconds
Started May 07 01:15:19 PM PDT 24
Finished May 07 01:15:23 PM PDT 24
Peak memory 215592 kb
Host smart-e4608192-7144-4249-a608-ddc7845365c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300553553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1300553553
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1544449403
Short name T131
Test name
Test status
Simulation time 61487333 ps
CPU time 3.96 seconds
Started May 07 01:15:22 PM PDT 24
Finished May 07 01:15:27 PM PDT 24
Peak memory 215804 kb
Host smart-ea89418d-8f94-482d-a852-a1a2018b5315
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544449403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1544449403
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.642537904
Short name T110
Test name
Test status
Simulation time 71138762 ps
CPU time 3.42 seconds
Started May 07 01:15:20 PM PDT 24
Finished May 07 01:15:25 PM PDT 24
Peak memory 218432 kb
Host smart-a84dd607-ff5c-4235-b0e7-b235d68eae05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642537904 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.642537904
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1203369299
Short name T825
Test name
Test status
Simulation time 102644424 ps
CPU time 1.27 seconds
Started May 07 01:15:21 PM PDT 24
Finished May 07 01:15:23 PM PDT 24
Peak memory 207344 kb
Host smart-b6d62846-2983-476a-9799-bb58f6b4cd6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203369299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1203369299
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3645486470
Short name T857
Test name
Test status
Simulation time 21667790 ps
CPU time 0.78 seconds
Started May 07 01:15:22 PM PDT 24
Finished May 07 01:15:24 PM PDT 24
Peak memory 203624 kb
Host smart-b24906a1-08bb-4a71-9275-9b7af81a5b90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645486470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3645486470
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.443242227
Short name T804
Test name
Test status
Simulation time 620652136 ps
CPU time 3.51 seconds
Started May 07 01:15:19 PM PDT 24
Finished May 07 01:15:24 PM PDT 24
Peak memory 215980 kb
Host smart-4dc3cd6d-0600-466a-9143-1b61f5b3782c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443242227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.443242227
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3854398514
Short name T768
Test name
Test status
Simulation time 109031855 ps
CPU time 7.42 seconds
Started May 07 01:15:19 PM PDT 24
Finished May 07 01:15:28 PM PDT 24
Peak memory 215588 kb
Host smart-87174a40-940d-4f30-a2c6-1722a84d1b5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854398514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3854398514
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3294080975
Short name T798
Test name
Test status
Simulation time 96217828 ps
CPU time 1.82 seconds
Started May 07 01:15:29 PM PDT 24
Finished May 07 01:15:32 PM PDT 24
Peak memory 215688 kb
Host smart-40a8478b-91b4-4b42-b353-be7594c7c457
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294080975 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3294080975
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.270438155
Short name T147
Test name
Test status
Simulation time 73526345 ps
CPU time 1.89 seconds
Started May 07 01:15:28 PM PDT 24
Finished May 07 01:15:30 PM PDT 24
Peak memory 215556 kb
Host smart-28002e5c-9560-485e-b759-f9e411388ac5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270438155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.270438155
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2466267566
Short name T835
Test name
Test status
Simulation time 15255852 ps
CPU time 0.7 seconds
Started May 07 01:15:25 PM PDT 24
Finished May 07 01:15:27 PM PDT 24
Peak memory 203576 kb
Host smart-64ef68f9-d757-449d-a4f6-ce299b0c1db6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466267566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2466267566
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1766057234
Short name T760
Test name
Test status
Simulation time 45604261 ps
CPU time 1.72 seconds
Started May 07 01:15:29 PM PDT 24
Finished May 07 01:15:33 PM PDT 24
Peak memory 215592 kb
Host smart-5aa23981-3fbf-4f9b-aca9-56e2cbfd304f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766057234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1766057234
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.288917431
Short name T819
Test name
Test status
Simulation time 270324913 ps
CPU time 4.03 seconds
Started May 07 01:15:20 PM PDT 24
Finished May 07 01:15:25 PM PDT 24
Peak memory 215668 kb
Host smart-483da3c7-eff8-437f-80bb-e5a6bfcf9429
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288917431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.288917431
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1012153339
Short name T814
Test name
Test status
Simulation time 120968949 ps
CPU time 7.51 seconds
Started May 07 01:15:20 PM PDT 24
Finished May 07 01:15:29 PM PDT 24
Peak memory 216008 kb
Host smart-130eda19-d823-4b62-880e-39af9e01223a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012153339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1012153339
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3240465683
Short name T757
Test name
Test status
Simulation time 610320434 ps
CPU time 3.06 seconds
Started May 07 01:15:29 PM PDT 24
Finished May 07 01:15:34 PM PDT 24
Peak memory 217632 kb
Host smart-ba062bf0-7555-4d80-a690-7e2980230fde
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240465683 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3240465683
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1529950719
Short name T150
Test name
Test status
Simulation time 105797455 ps
CPU time 2.55 seconds
Started May 07 01:15:26 PM PDT 24
Finished May 07 01:15:29 PM PDT 24
Peak memory 207324 kb
Host smart-e01479a3-8141-4012-9219-db6c50e30ea4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529950719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1529950719
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1827028530
Short name T795
Test name
Test status
Simulation time 41628554 ps
CPU time 0.69 seconds
Started May 07 01:15:27 PM PDT 24
Finished May 07 01:15:29 PM PDT 24
Peak memory 203560 kb
Host smart-689e3ba5-c9f1-406d-8512-71452a8f4d7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827028530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1827028530
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1582322599
Short name T161
Test name
Test status
Simulation time 148553426 ps
CPU time 2.08 seconds
Started May 07 01:15:27 PM PDT 24
Finished May 07 01:15:30 PM PDT 24
Peak memory 207388 kb
Host smart-5e185d3b-4339-40b5-b354-bc34be3befb5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582322599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1582322599
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.4076958650
Short name T794
Test name
Test status
Simulation time 308166465 ps
CPU time 2.35 seconds
Started May 07 01:15:29 PM PDT 24
Finished May 07 01:15:32 PM PDT 24
Peak memory 215652 kb
Host smart-64648e2e-43ce-44d4-aae7-b12cc8f14c5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076958650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
4076958650
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3030288841
Short name T806
Test name
Test status
Simulation time 318493381 ps
CPU time 1.91 seconds
Started May 07 01:15:26 PM PDT 24
Finished May 07 01:15:29 PM PDT 24
Peak memory 215844 kb
Host smart-809159b4-0142-4364-8f08-f7defe7a7f2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030288841 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3030288841
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.639740167
Short name T782
Test name
Test status
Simulation time 48173214 ps
CPU time 1.71 seconds
Started May 07 01:15:29 PM PDT 24
Finished May 07 01:15:32 PM PDT 24
Peak memory 215584 kb
Host smart-43d8f471-2e33-4356-8b00-9d35c7465f1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639740167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.639740167
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.4048396418
Short name T754
Test name
Test status
Simulation time 42699522 ps
CPU time 0.75 seconds
Started May 07 01:15:29 PM PDT 24
Finished May 07 01:15:30 PM PDT 24
Peak memory 203624 kb
Host smart-e8672395-1ec7-4fe0-8d7e-b1dce5062120
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048396418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
4048396418
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.759425003
Short name T784
Test name
Test status
Simulation time 77735813 ps
CPU time 2.69 seconds
Started May 07 01:15:28 PM PDT 24
Finished May 07 01:15:32 PM PDT 24
Peak memory 215580 kb
Host smart-08274266-dff9-4fa3-9b7e-2e6e27cc9490
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759425003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.759425003
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3011789891
Short name T112
Test name
Test status
Simulation time 86028194 ps
CPU time 2.52 seconds
Started May 07 01:15:29 PM PDT 24
Finished May 07 01:15:33 PM PDT 24
Peak memory 216804 kb
Host smart-d5753720-88fe-4875-8151-06a08b990b06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011789891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3011789891
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.4226728769
Short name T134
Test name
Test status
Simulation time 319703407 ps
CPU time 7.13 seconds
Started May 07 01:15:28 PM PDT 24
Finished May 07 01:15:36 PM PDT 24
Peak memory 215524 kb
Host smart-167c4d8c-7bde-4b4c-a5d0-4420757a1548
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226728769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.4226728769
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3206558197
Short name T120
Test name
Test status
Simulation time 257428917 ps
CPU time 3.49 seconds
Started May 07 01:15:30 PM PDT 24
Finished May 07 01:15:35 PM PDT 24
Peak memory 217836 kb
Host smart-2c1ebcd1-4dc8-42da-aaa6-6b09deca409b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206558197 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3206558197
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1653530044
Short name T830
Test name
Test status
Simulation time 134944676 ps
CPU time 2.51 seconds
Started May 07 01:15:30 PM PDT 24
Finished May 07 01:15:34 PM PDT 24
Peak memory 215312 kb
Host smart-5d31a68f-93c6-4ff9-8352-bd8c5b3bea4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653530044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1653530044
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1823221701
Short name T151
Test name
Test status
Simulation time 693723858 ps
CPU time 4.07 seconds
Started May 07 01:15:28 PM PDT 24
Finished May 07 01:15:33 PM PDT 24
Peak memory 215560 kb
Host smart-caa40f38-9010-4a26-b5df-1a80529687d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823221701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1823221701
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1424881380
Short name T124
Test name
Test status
Simulation time 271860686 ps
CPU time 3.33 seconds
Started May 07 01:15:27 PM PDT 24
Finished May 07 01:15:31 PM PDT 24
Peak memory 216632 kb
Host smart-e7ab6e00-1fcb-433e-916b-5b3570278ae9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424881380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
1424881380
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.139069553
Short name T40
Test name
Test status
Simulation time 407002526 ps
CPU time 7.05 seconds
Started May 07 01:15:27 PM PDT 24
Finished May 07 01:15:35 PM PDT 24
Peak memory 215600 kb
Host smart-353d801e-7921-453f-ae5d-1b76306b7533
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139069553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.139069553
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2938169107
Short name T810
Test name
Test status
Simulation time 133890453 ps
CPU time 3.57 seconds
Started May 07 01:15:35 PM PDT 24
Finished May 07 01:15:40 PM PDT 24
Peak memory 216960 kb
Host smart-75ad9108-84c5-414b-9dd3-8274a9283090
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938169107 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2938169107
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.4285190195
Short name T824
Test name
Test status
Simulation time 59984158 ps
CPU time 1.76 seconds
Started May 07 01:15:26 PM PDT 24
Finished May 07 01:15:28 PM PDT 24
Peak memory 207360 kb
Host smart-b72a1d33-45ad-4003-ac10-c5624d2addf8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285190195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
4285190195
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2314041487
Short name T748
Test name
Test status
Simulation time 11402926 ps
CPU time 0.72 seconds
Started May 07 01:15:27 PM PDT 24
Finished May 07 01:15:29 PM PDT 24
Peak memory 203532 kb
Host smart-484435ba-d108-4029-b4a2-2a43ddf7612d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314041487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2314041487
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1595536168
Short name T807
Test name
Test status
Simulation time 997488115 ps
CPU time 2.86 seconds
Started May 07 01:15:28 PM PDT 24
Finished May 07 01:15:32 PM PDT 24
Peak memory 215604 kb
Host smart-94c173b7-0c6d-4f22-80ab-b98ea3f57360
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595536168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1595536168
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.27690447
Short name T132
Test name
Test status
Simulation time 172277521 ps
CPU time 4.22 seconds
Started May 07 01:15:27 PM PDT 24
Finished May 07 01:15:32 PM PDT 24
Peak memory 215660 kb
Host smart-cd5179fe-af07-4a95-b4eb-a5cda78dd0a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27690447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.27690447
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1650296349
Short name T776
Test name
Test status
Simulation time 103844292 ps
CPU time 2.22 seconds
Started May 07 01:15:35 PM PDT 24
Finished May 07 01:15:39 PM PDT 24
Peak memory 216872 kb
Host smart-b0f8fd8a-228d-4965-9a8a-9da61a59a59f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650296349 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1650296349
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2397265280
Short name T149
Test name
Test status
Simulation time 656442506 ps
CPU time 1.36 seconds
Started May 07 01:15:38 PM PDT 24
Finished May 07 01:15:41 PM PDT 24
Peak memory 207348 kb
Host smart-68f0fab7-80f2-4abd-9049-9642bc60ea12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397265280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2397265280
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1065206022
Short name T755
Test name
Test status
Simulation time 23179492 ps
CPU time 0.76 seconds
Started May 07 01:15:34 PM PDT 24
Finished May 07 01:15:35 PM PDT 24
Peak memory 203920 kb
Host smart-f955470b-4fc3-44c6-ba1b-9d731f269ac1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065206022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1065206022
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.702416659
Short name T852
Test name
Test status
Simulation time 661330765 ps
CPU time 4.52 seconds
Started May 07 01:15:34 PM PDT 24
Finished May 07 01:15:40 PM PDT 24
Peak memory 215592 kb
Host smart-e11e8762-c3ac-4675-be34-c0a12eca608c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702416659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.702416659
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2161210848
Short name T843
Test name
Test status
Simulation time 433401820 ps
CPU time 5.25 seconds
Started May 07 01:15:35 PM PDT 24
Finished May 07 01:15:41 PM PDT 24
Peak memory 215608 kb
Host smart-620665b8-6ceb-4dcc-8e0a-9f2fa135d1eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161210848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2161210848
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2269136511
Short name T116
Test name
Test status
Simulation time 545486268 ps
CPU time 13.11 seconds
Started May 07 01:15:35 PM PDT 24
Finished May 07 01:15:49 PM PDT 24
Peak memory 215876 kb
Host smart-ba79a026-6439-4fac-88d7-7c45812789e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269136511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2269136511
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2076717953
Short name T823
Test name
Test status
Simulation time 331762695 ps
CPU time 20.29 seconds
Started May 07 01:14:53 PM PDT 24
Finished May 07 01:15:15 PM PDT 24
Peak memory 215552 kb
Host smart-61c6abcd-5bda-4cbd-ab0c-76b30039fa1d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076717953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2076717953
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1552148939
Short name T142
Test name
Test status
Simulation time 543286358 ps
CPU time 35.74 seconds
Started May 07 01:14:57 PM PDT 24
Finished May 07 01:15:33 PM PDT 24
Peak memory 207272 kb
Host smart-dce60b84-37c1-4b91-a4b9-237dc97a7609
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552148939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1552148939
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.4215106903
Short name T96
Test name
Test status
Simulation time 41383020 ps
CPU time 1.36 seconds
Started May 07 01:14:52 PM PDT 24
Finished May 07 01:14:55 PM PDT 24
Peak memory 216556 kb
Host smart-d23715d2-e0b6-48ed-9989-89deab417da4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215106903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.4215106903
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3180997020
Short name T815
Test name
Test status
Simulation time 160441690 ps
CPU time 3.94 seconds
Started May 07 01:14:55 PM PDT 24
Finished May 07 01:15:00 PM PDT 24
Peak memory 218188 kb
Host smart-e6a515ba-b65b-4918-82d2-797df088800d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180997020 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3180997020
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2099268086
Short name T829
Test name
Test status
Simulation time 132405688 ps
CPU time 1.89 seconds
Started May 07 01:15:00 PM PDT 24
Finished May 07 01:15:03 PM PDT 24
Peak memory 215528 kb
Host smart-99f486d2-32d7-4a66-a51d-b18c32cbf60e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099268086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
099268086
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2610391118
Short name T374
Test name
Test status
Simulation time 54708931 ps
CPU time 0.73 seconds
Started May 07 01:14:57 PM PDT 24
Finished May 07 01:14:59 PM PDT 24
Peak memory 203656 kb
Host smart-6162cfcb-7361-4f2d-8a39-037a85bcc5d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610391118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
610391118
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2663132639
Short name T140
Test name
Test status
Simulation time 22881896 ps
CPU time 1.66 seconds
Started May 07 01:14:55 PM PDT 24
Finished May 07 01:14:57 PM PDT 24
Peak memory 215672 kb
Host smart-0c3f4fc8-5225-428c-a6f1-f625dcbed5a9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663132639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2663132639
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3833981666
Short name T779
Test name
Test status
Simulation time 30894214 ps
CPU time 0.67 seconds
Started May 07 01:14:52 PM PDT 24
Finished May 07 01:14:54 PM PDT 24
Peak memory 203984 kb
Host smart-7de3e161-7a83-4137-b085-40bac97d1ece
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833981666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3833981666
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1135910631
Short name T775
Test name
Test status
Simulation time 67363527 ps
CPU time 1.7 seconds
Started May 07 01:14:56 PM PDT 24
Finished May 07 01:14:58 PM PDT 24
Peak memory 215596 kb
Host smart-eda2b12a-a474-4358-a3a1-9eb683cde4fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135910631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1135910631
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.4255801912
Short name T129
Test name
Test status
Simulation time 885744136 ps
CPU time 4.56 seconds
Started May 07 01:14:53 PM PDT 24
Finished May 07 01:14:59 PM PDT 24
Peak memory 216720 kb
Host smart-2103471b-6096-412c-8c5f-8ca55db8614d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255801912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.4
255801912
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.105971127
Short name T135
Test name
Test status
Simulation time 379379770 ps
CPU time 19.49 seconds
Started May 07 01:14:52 PM PDT 24
Finished May 07 01:15:13 PM PDT 24
Peak memory 216300 kb
Host smart-d552f14c-685c-4116-973b-9857fe4b4128
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105971127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.105971127
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1243150330
Short name T809
Test name
Test status
Simulation time 43031936 ps
CPU time 0.7 seconds
Started May 07 01:15:37 PM PDT 24
Finished May 07 01:15:39 PM PDT 24
Peak memory 203912 kb
Host smart-fdcebdfd-cfb9-4d38-bc65-ef26a5130260
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243150330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1243150330
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3730790594
Short name T848
Test name
Test status
Simulation time 23541739 ps
CPU time 0.75 seconds
Started May 07 01:15:36 PM PDT 24
Finished May 07 01:15:38 PM PDT 24
Peak memory 203616 kb
Host smart-09f788e9-9dd0-4442-a314-f7e1c1a3376d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730790594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3730790594
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1324205213
Short name T781
Test name
Test status
Simulation time 14634579 ps
CPU time 0.69 seconds
Started May 07 01:15:35 PM PDT 24
Finished May 07 01:15:37 PM PDT 24
Peak memory 203476 kb
Host smart-b97416e9-5dbb-4842-a7e6-673880b7cc23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324205213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1324205213
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2072363997
Short name T845
Test name
Test status
Simulation time 56088477 ps
CPU time 0.72 seconds
Started May 07 01:15:36 PM PDT 24
Finished May 07 01:15:39 PM PDT 24
Peak memory 203572 kb
Host smart-6aae9c0a-4a3a-49d9-b3a9-b835b3420fc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072363997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2072363997
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.4008459364
Short name T764
Test name
Test status
Simulation time 44702696 ps
CPU time 0.69 seconds
Started May 07 01:15:35 PM PDT 24
Finished May 07 01:15:37 PM PDT 24
Peak memory 203552 kb
Host smart-8d147adc-b42b-45ee-9396-ad2b780d9588
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008459364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
4008459364
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1075703937
Short name T796
Test name
Test status
Simulation time 10455660 ps
CPU time 0.71 seconds
Started May 07 01:15:36 PM PDT 24
Finished May 07 01:15:38 PM PDT 24
Peak memory 203588 kb
Host smart-535cda0a-802b-44a0-9e89-ea94c6f6babd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075703937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1075703937
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.802768629
Short name T769
Test name
Test status
Simulation time 12521065 ps
CPU time 0.76 seconds
Started May 07 01:15:36 PM PDT 24
Finished May 07 01:15:39 PM PDT 24
Peak memory 203680 kb
Host smart-7908c99b-db3b-42c3-8878-2454262e77ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802768629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.802768629
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3303546383
Short name T771
Test name
Test status
Simulation time 11615508 ps
CPU time 0.77 seconds
Started May 07 01:15:34 PM PDT 24
Finished May 07 01:15:36 PM PDT 24
Peak memory 203828 kb
Host smart-bd11209f-cb46-410f-99ce-659a9d8cbaba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303546383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3303546383
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1656396850
Short name T850
Test name
Test status
Simulation time 17542047 ps
CPU time 0.74 seconds
Started May 07 01:15:36 PM PDT 24
Finished May 07 01:15:38 PM PDT 24
Peak memory 203668 kb
Host smart-1b6b02ff-5b8f-4275-a655-80634cd7e10c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656396850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1656396850
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2667178649
Short name T770
Test name
Test status
Simulation time 12884942 ps
CPU time 0.7 seconds
Started May 07 01:15:36 PM PDT 24
Finished May 07 01:15:38 PM PDT 24
Peak memory 203920 kb
Host smart-5987ae62-1ba5-432d-9913-ab101e432851
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667178649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2667178649
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.894846478
Short name T826
Test name
Test status
Simulation time 4790613746 ps
CPU time 24.24 seconds
Started May 07 01:15:03 PM PDT 24
Finished May 07 01:15:29 PM PDT 24
Peak memory 215584 kb
Host smart-7350dbf2-666d-4625-8032-e50505dcb75a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894846478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.894846478
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3470935473
Short name T160
Test name
Test status
Simulation time 1633009860 ps
CPU time 24.65 seconds
Started May 07 01:15:02 PM PDT 24
Finished May 07 01:15:28 PM PDT 24
Peak memory 207228 kb
Host smart-c6584ae3-c80b-40ad-b344-5f2e9356af58
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470935473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3470935473
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.4081528222
Short name T94
Test name
Test status
Simulation time 39848055 ps
CPU time 1.43 seconds
Started May 07 01:14:52 PM PDT 24
Finished May 07 01:14:55 PM PDT 24
Peak memory 207380 kb
Host smart-cc1cfdfc-9b17-4b67-b4bf-2b5fd4cc3b0c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081528222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.4081528222
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.70136106
Short name T766
Test name
Test status
Simulation time 47652602 ps
CPU time 1.51 seconds
Started May 07 01:15:03 PM PDT 24
Finished May 07 01:15:06 PM PDT 24
Peak memory 215624 kb
Host smart-cd01145b-8727-4d7d-9dd7-9413a7241d2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70136106 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.70136106
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.826815111
Short name T762
Test name
Test status
Simulation time 73886023 ps
CPU time 2.31 seconds
Started May 07 01:14:52 PM PDT 24
Finished May 07 01:14:56 PM PDT 24
Peak memory 215520 kb
Host smart-b65dd9fd-8d1a-4bef-a39e-91ee5975cca8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826815111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.826815111
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1199379647
Short name T751
Test name
Test status
Simulation time 13825701 ps
CPU time 0.7 seconds
Started May 07 01:14:54 PM PDT 24
Finished May 07 01:14:56 PM PDT 24
Peak memory 203624 kb
Host smart-3c893160-45bc-40de-98b3-ebe0ee67205e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199379647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
199379647
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.719805476
Short name T138
Test name
Test status
Simulation time 20180326 ps
CPU time 1.22 seconds
Started May 07 01:14:53 PM PDT 24
Finished May 07 01:14:55 PM PDT 24
Peak memory 215660 kb
Host smart-b6f395b6-7d15-4a92-9848-0747bc7ac13a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719805476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.719805476
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3369864426
Short name T834
Test name
Test status
Simulation time 25912761 ps
CPU time 0.65 seconds
Started May 07 01:14:59 PM PDT 24
Finished May 07 01:15:00 PM PDT 24
Peak memory 203636 kb
Host smart-a02deaf2-d55a-493a-a3b6-47286be40b34
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369864426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3369864426
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.130234827
Short name T767
Test name
Test status
Simulation time 108127043 ps
CPU time 1.64 seconds
Started May 07 01:15:04 PM PDT 24
Finished May 07 01:15:07 PM PDT 24
Peak memory 207260 kb
Host smart-ca9aa0e1-d0fe-42af-b196-7e8a0130de7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130234827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.130234827
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1763251927
Short name T128
Test name
Test status
Simulation time 315855617 ps
CPU time 2.55 seconds
Started May 07 01:14:54 PM PDT 24
Finished May 07 01:14:58 PM PDT 24
Peak memory 215632 kb
Host smart-5e24a1b2-b1e2-4bae-bcd3-6afd48f70abe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763251927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
763251927
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3625841194
Short name T813
Test name
Test status
Simulation time 777061365 ps
CPU time 6.43 seconds
Started May 07 01:14:57 PM PDT 24
Finished May 07 01:15:04 PM PDT 24
Peak memory 215604 kb
Host smart-2f0b3141-3caa-418b-881a-6a3738baf90c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625841194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3625841194
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2402275509
Short name T772
Test name
Test status
Simulation time 11232734 ps
CPU time 0.75 seconds
Started May 07 01:15:42 PM PDT 24
Finished May 07 01:15:44 PM PDT 24
Peak memory 203632 kb
Host smart-e8296270-a76d-42d7-b45a-911c881d9ee3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402275509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2402275509
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2858728527
Short name T780
Test name
Test status
Simulation time 39522004 ps
CPU time 0.75 seconds
Started May 07 01:15:36 PM PDT 24
Finished May 07 01:15:38 PM PDT 24
Peak memory 203668 kb
Host smart-c30db32c-78a2-422f-b3fe-f680084ddfbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858728527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
2858728527
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1257699635
Short name T822
Test name
Test status
Simulation time 21146009 ps
CPU time 0.8 seconds
Started May 07 01:15:36 PM PDT 24
Finished May 07 01:15:38 PM PDT 24
Peak memory 203668 kb
Host smart-49e2dd8a-23bc-46cc-8175-dd6b4c5e73ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257699635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
1257699635
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.4210116906
Short name T800
Test name
Test status
Simulation time 13891130 ps
CPU time 0.72 seconds
Started May 07 01:15:35 PM PDT 24
Finished May 07 01:15:37 PM PDT 24
Peak memory 203568 kb
Host smart-716c9ab9-d33e-47f4-b9d1-995da4f9f025
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210116906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
4210116906
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2189477435
Short name T802
Test name
Test status
Simulation time 37484758 ps
CPU time 0.75 seconds
Started May 07 01:15:36 PM PDT 24
Finished May 07 01:15:38 PM PDT 24
Peak memory 203916 kb
Host smart-2f8c612a-469a-4e8f-8711-858a76d994fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189477435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2189477435
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2746593579
Short name T763
Test name
Test status
Simulation time 18133936 ps
CPU time 0.76 seconds
Started May 07 01:15:38 PM PDT 24
Finished May 07 01:15:41 PM PDT 24
Peak memory 203656 kb
Host smart-200f526e-80e0-4bf6-9577-85ad77c7c661
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746593579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2746593579
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.4571302
Short name T756
Test name
Test status
Simulation time 23430244 ps
CPU time 0.73 seconds
Started May 07 01:15:36 PM PDT 24
Finished May 07 01:15:39 PM PDT 24
Peak memory 203720 kb
Host smart-31b254f6-3396-4bc5-950e-50d39613691d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4571302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.4571302
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2381579633
Short name T749
Test name
Test status
Simulation time 49495111 ps
CPU time 0.75 seconds
Started May 07 01:15:36 PM PDT 24
Finished May 07 01:15:39 PM PDT 24
Peak memory 203596 kb
Host smart-c13f3cec-2763-49eb-8f36-4fc3e5b932bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381579633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2381579633
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1844243542
Short name T747
Test name
Test status
Simulation time 183143107 ps
CPU time 0.75 seconds
Started May 07 01:15:38 PM PDT 24
Finished May 07 01:15:40 PM PDT 24
Peak memory 203664 kb
Host smart-59ac82f0-fccc-441e-90c2-cf3f0d8ba485
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844243542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1844243542
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2305514071
Short name T785
Test name
Test status
Simulation time 44172844 ps
CPU time 0.73 seconds
Started May 07 01:15:36 PM PDT 24
Finished May 07 01:15:38 PM PDT 24
Peak memory 203680 kb
Host smart-b0cc0b4a-d65d-4fa5-8c57-e707e3521ac4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305514071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2305514071
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1792813682
Short name T854
Test name
Test status
Simulation time 1549824905 ps
CPU time 8.39 seconds
Started May 07 01:15:06 PM PDT 24
Finished May 07 01:15:15 PM PDT 24
Peak memory 215496 kb
Host smart-574f80e3-fb84-44e3-a9de-4da4d05ca38c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792813682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1792813682
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2412816472
Short name T778
Test name
Test status
Simulation time 649084041 ps
CPU time 13.82 seconds
Started May 07 01:15:03 PM PDT 24
Finished May 07 01:15:18 PM PDT 24
Peak memory 207264 kb
Host smart-ef4a7bd2-b46b-410a-83b9-347f089dd329
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412816472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2412816472
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3579701755
Short name T803
Test name
Test status
Simulation time 33461043 ps
CPU time 1.27 seconds
Started May 07 01:15:02 PM PDT 24
Finished May 07 01:15:04 PM PDT 24
Peak memory 207296 kb
Host smart-fd0850a3-6429-4f4f-8acd-c72a9bac3488
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579701755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3579701755
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1007497584
Short name T808
Test name
Test status
Simulation time 50317966 ps
CPU time 1.73 seconds
Started May 07 01:15:01 PM PDT 24
Finished May 07 01:15:04 PM PDT 24
Peak memory 215696 kb
Host smart-f747a2a6-b814-4abd-b0f5-578252d86542
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007497584 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1007497584
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.525392029
Short name T39
Test name
Test status
Simulation time 168017561 ps
CPU time 2.65 seconds
Started May 07 01:15:01 PM PDT 24
Finished May 07 01:15:05 PM PDT 24
Peak memory 215556 kb
Host smart-798c4b54-87e2-4907-9051-bb31285f61f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525392029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.525392029
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1905084956
Short name T791
Test name
Test status
Simulation time 30934712 ps
CPU time 0.76 seconds
Started May 07 01:15:03 PM PDT 24
Finished May 07 01:15:05 PM PDT 24
Peak memory 203660 kb
Host smart-9a3e69fa-a220-4ba3-9e55-817e73d80989
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905084956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
905084956
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3255755557
Short name T141
Test name
Test status
Simulation time 395305569 ps
CPU time 2 seconds
Started May 07 01:15:01 PM PDT 24
Finished May 07 01:15:04 PM PDT 24
Peak memory 215740 kb
Host smart-0aff89ad-320b-44a5-9ba8-52cbaaf8181c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255755557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3255755557
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3422407960
Short name T758
Test name
Test status
Simulation time 41429095 ps
CPU time 0.71 seconds
Started May 07 01:15:01 PM PDT 24
Finished May 07 01:15:03 PM PDT 24
Peak memory 203636 kb
Host smart-73a757c0-c126-4691-9baa-79d69b2e3b9e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422407960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3422407960
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2118380224
Short name T162
Test name
Test status
Simulation time 80477564 ps
CPU time 1.92 seconds
Started May 07 01:15:02 PM PDT 24
Finished May 07 01:15:05 PM PDT 24
Peak memory 215624 kb
Host smart-c0d6d60c-b3db-4060-b0ac-dabc7d61644c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118380224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2118380224
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1583047907
Short name T125
Test name
Test status
Simulation time 20626983 ps
CPU time 1.3 seconds
Started May 07 01:15:03 PM PDT 24
Finished May 07 01:15:05 PM PDT 24
Peak memory 215596 kb
Host smart-5713253e-b4a8-4eb4-83b3-ee89ab9e8d11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583047907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
583047907
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.738848696
Short name T788
Test name
Test status
Simulation time 1991862757 ps
CPU time 7.14 seconds
Started May 07 01:15:02 PM PDT 24
Finished May 07 01:15:10 PM PDT 24
Peak memory 215660 kb
Host smart-eb310961-65c4-4cef-af64-90848af26036
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738848696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.738848696
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.847415886
Short name T773
Test name
Test status
Simulation time 15362310 ps
CPU time 0.73 seconds
Started May 07 01:15:38 PM PDT 24
Finished May 07 01:15:40 PM PDT 24
Peak memory 203924 kb
Host smart-502db5fa-8b3f-409c-a1fd-47fe5b276676
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847415886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.847415886
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1686327537
Short name T849
Test name
Test status
Simulation time 14072579 ps
CPU time 0.75 seconds
Started May 07 01:15:36 PM PDT 24
Finished May 07 01:15:38 PM PDT 24
Peak memory 203548 kb
Host smart-c88089ef-d778-4df3-ae38-68273294ebe7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686327537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1686327537
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.4279135853
Short name T165
Test name
Test status
Simulation time 14692390 ps
CPU time 0.74 seconds
Started May 07 01:15:37 PM PDT 24
Finished May 07 01:15:39 PM PDT 24
Peak memory 203648 kb
Host smart-f0b39018-8deb-4149-8762-fd3af0cd625a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279135853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
4279135853
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1827670786
Short name T750
Test name
Test status
Simulation time 18568119 ps
CPU time 0.73 seconds
Started May 07 01:15:33 PM PDT 24
Finished May 07 01:15:34 PM PDT 24
Peak memory 203648 kb
Host smart-943cf72d-da79-4dfe-9931-2e05dafa53a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827670786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1827670786
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.332674519
Short name T753
Test name
Test status
Simulation time 31277082 ps
CPU time 0.68 seconds
Started May 07 01:15:33 PM PDT 24
Finished May 07 01:15:35 PM PDT 24
Peak memory 203648 kb
Host smart-b31aff9d-92a0-48da-9297-1b52f1d01856
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332674519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.332674519
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3585651553
Short name T746
Test name
Test status
Simulation time 43973492 ps
CPU time 0.82 seconds
Started May 07 01:15:35 PM PDT 24
Finished May 07 01:15:37 PM PDT 24
Peak memory 203644 kb
Host smart-33b7229a-a3d4-483e-951c-9d9526b306fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585651553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3585651553
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3304676417
Short name T797
Test name
Test status
Simulation time 14103612 ps
CPU time 0.72 seconds
Started May 07 01:15:37 PM PDT 24
Finished May 07 01:15:40 PM PDT 24
Peak memory 203616 kb
Host smart-27d8973a-c422-4166-87fe-34e7f4e5ddb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304676417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3304676417
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3562382415
Short name T783
Test name
Test status
Simulation time 22908467 ps
CPU time 0.69 seconds
Started May 07 01:15:42 PM PDT 24
Finished May 07 01:15:43 PM PDT 24
Peak memory 203892 kb
Host smart-18170c89-2a2c-433a-92c4-4a8bf3187cd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562382415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3562382415
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.317972067
Short name T743
Test name
Test status
Simulation time 12705949 ps
CPU time 0.68 seconds
Started May 07 01:15:35 PM PDT 24
Finished May 07 01:15:37 PM PDT 24
Peak memory 203428 kb
Host smart-7a6ddf15-a220-46ab-9f20-4b560493685a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317972067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.317972067
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3464496384
Short name T832
Test name
Test status
Simulation time 134576464 ps
CPU time 2.37 seconds
Started May 07 01:15:13 PM PDT 24
Finished May 07 01:15:16 PM PDT 24
Peak memory 216740 kb
Host smart-4fd57fba-c451-4a18-99f7-33e2b46044ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464496384 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3464496384
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1143006970
Short name T145
Test name
Test status
Simulation time 91912423 ps
CPU time 2.45 seconds
Started May 07 01:15:09 PM PDT 24
Finished May 07 01:15:12 PM PDT 24
Peak memory 215532 kb
Host smart-f20e6373-76da-414f-b685-211339560d01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143006970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
143006970
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.955291331
Short name T846
Test name
Test status
Simulation time 34523267 ps
CPU time 0.8 seconds
Started May 07 01:15:11 PM PDT 24
Finished May 07 01:15:13 PM PDT 24
Peak memory 203656 kb
Host smart-ab3606da-616f-4e0d-94f0-e4a98d69528f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955291331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.955291331
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1826824651
Short name T154
Test name
Test status
Simulation time 128170529 ps
CPU time 2.99 seconds
Started May 07 01:15:10 PM PDT 24
Finished May 07 01:15:13 PM PDT 24
Peak memory 215564 kb
Host smart-ebc209b9-6714-4094-914e-05238b22b92d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826824651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1826824651
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2354709219
Short name T380
Test name
Test status
Simulation time 7186673518 ps
CPU time 16.68 seconds
Started May 07 01:15:12 PM PDT 24
Finished May 07 01:15:30 PM PDT 24
Peak memory 215840 kb
Host smart-d64a4863-7c12-47bf-91de-0ca34b43d190
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354709219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2354709219
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3409886490
Short name T789
Test name
Test status
Simulation time 56439947 ps
CPU time 3.51 seconds
Started May 07 01:15:10 PM PDT 24
Finished May 07 01:15:15 PM PDT 24
Peak memory 218348 kb
Host smart-32e25dee-7abf-4d59-bf36-179f71962809
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409886490 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3409886490
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2858557665
Short name T840
Test name
Test status
Simulation time 77460999 ps
CPU time 1.39 seconds
Started May 07 01:15:11 PM PDT 24
Finished May 07 01:15:14 PM PDT 24
Peak memory 207312 kb
Host smart-30577fa9-8c62-43f7-aa66-fe77990722f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858557665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
858557665
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1956112550
Short name T777
Test name
Test status
Simulation time 16929059 ps
CPU time 0.71 seconds
Started May 07 01:15:11 PM PDT 24
Finished May 07 01:15:13 PM PDT 24
Peak memory 203568 kb
Host smart-679b679b-31f6-433f-bd08-a841415a3545
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956112550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
956112550
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3946275095
Short name T818
Test name
Test status
Simulation time 81884249 ps
CPU time 2.73 seconds
Started May 07 01:15:11 PM PDT 24
Finished May 07 01:15:15 PM PDT 24
Peak memory 215644 kb
Host smart-273c50a1-92d7-41df-96f1-eaa2dea3c559
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946275095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3946275095
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1989932805
Short name T844
Test name
Test status
Simulation time 560900893 ps
CPU time 4.04 seconds
Started May 07 01:15:12 PM PDT 24
Finished May 07 01:15:18 PM PDT 24
Peak memory 215624 kb
Host smart-4f63762a-7447-4a18-8faa-41b49c806c0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989932805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
989932805
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.412184261
Short name T381
Test name
Test status
Simulation time 1241643774 ps
CPU time 12.9 seconds
Started May 07 01:15:10 PM PDT 24
Finished May 07 01:15:25 PM PDT 24
Peak memory 215804 kb
Host smart-163a1956-8afc-4fc1-b0a3-aca7324d6b4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412184261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.412184261
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3096486992
Short name T123
Test name
Test status
Simulation time 182039153 ps
CPU time 2.6 seconds
Started May 07 01:15:11 PM PDT 24
Finished May 07 01:15:15 PM PDT 24
Peak memory 216976 kb
Host smart-9c6543b4-cd21-4cdf-8235-ac589a04d972
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096486992 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3096486992
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.4112547872
Short name T827
Test name
Test status
Simulation time 260153867 ps
CPU time 2.15 seconds
Started May 07 01:15:11 PM PDT 24
Finished May 07 01:15:15 PM PDT 24
Peak memory 207488 kb
Host smart-3d2e6cee-af55-43db-8365-800bf658577e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112547872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.4
112547872
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3292836998
Short name T765
Test name
Test status
Simulation time 15559549 ps
CPU time 0.72 seconds
Started May 07 01:15:10 PM PDT 24
Finished May 07 01:15:12 PM PDT 24
Peak memory 203656 kb
Host smart-41470648-9cb3-4a35-af41-199609ed4c83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292836998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
292836998
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.758137095
Short name T153
Test name
Test status
Simulation time 446142632 ps
CPU time 3.17 seconds
Started May 07 01:15:10 PM PDT 24
Finished May 07 01:15:15 PM PDT 24
Peak memory 215656 kb
Host smart-2890d7c4-4802-475e-8237-7a4b06798a47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758137095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.758137095
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3240292568
Short name T109
Test name
Test status
Simulation time 48440055 ps
CPU time 1.42 seconds
Started May 07 01:15:10 PM PDT 24
Finished May 07 01:15:12 PM PDT 24
Peak memory 215756 kb
Host smart-e6348e21-45e5-4d0d-8442-d3b98c818cba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240292568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
240292568
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2123064571
Short name T836
Test name
Test status
Simulation time 2021937822 ps
CPU time 18.61 seconds
Started May 07 01:15:11 PM PDT 24
Finished May 07 01:15:31 PM PDT 24
Peak memory 215712 kb
Host smart-f30d6919-384e-4588-8bb2-5538281f1d34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123064571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2123064571
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3530739586
Short name T799
Test name
Test status
Simulation time 142688815 ps
CPU time 2.96 seconds
Started May 07 01:15:10 PM PDT 24
Finished May 07 01:15:14 PM PDT 24
Peak memory 218028 kb
Host smart-f460530d-37fb-4796-8284-aced9fea699d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530739586 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3530739586
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.283630172
Short name T833
Test name
Test status
Simulation time 101777176 ps
CPU time 1.92 seconds
Started May 07 01:15:13 PM PDT 24
Finished May 07 01:15:16 PM PDT 24
Peak memory 215532 kb
Host smart-a3148c6f-0c39-416b-9dd0-0d393b5ebe4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283630172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.283630172
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2446442287
Short name T801
Test name
Test status
Simulation time 14515363 ps
CPU time 0.7 seconds
Started May 07 01:15:11 PM PDT 24
Finished May 07 01:15:14 PM PDT 24
Peak memory 203572 kb
Host smart-9b0edcb3-049c-455a-9a21-6ded8bbaa51e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446442287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
446442287
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1453874518
Short name T853
Test name
Test status
Simulation time 204002741 ps
CPU time 4.31 seconds
Started May 07 01:15:11 PM PDT 24
Finished May 07 01:15:17 PM PDT 24
Peak memory 215540 kb
Host smart-884b3f36-0d21-4c1a-b32f-40ed6e2153c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453874518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1453874518
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1465050601
Short name T127
Test name
Test status
Simulation time 97663757 ps
CPU time 1.91 seconds
Started May 07 01:15:11 PM PDT 24
Finished May 07 01:15:14 PM PDT 24
Peak memory 215696 kb
Host smart-fe63a95d-147f-4766-a621-8e21fb1ee5c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465050601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
465050601
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2123614018
Short name T164
Test name
Test status
Simulation time 720979194 ps
CPU time 15.18 seconds
Started May 07 01:15:11 PM PDT 24
Finished May 07 01:15:28 PM PDT 24
Peak memory 215776 kb
Host smart-097b7794-05ae-418a-a764-c765152f383f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123614018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2123614018
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2811065599
Short name T133
Test name
Test status
Simulation time 195085295 ps
CPU time 1.72 seconds
Started May 07 01:15:12 PM PDT 24
Finished May 07 01:15:15 PM PDT 24
Peak memory 215772 kb
Host smart-7fc48b2c-5dd7-4166-bc83-f7487262ca17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811065599 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2811065599
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2092945424
Short name T144
Test name
Test status
Simulation time 137840660 ps
CPU time 2.45 seconds
Started May 07 01:15:11 PM PDT 24
Finished May 07 01:15:15 PM PDT 24
Peak memory 215512 kb
Host smart-04ecda2f-8e12-4e22-9fef-fb49d766c700
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092945424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
092945424
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.700475580
Short name T817
Test name
Test status
Simulation time 12337862 ps
CPU time 0.76 seconds
Started May 07 01:15:12 PM PDT 24
Finished May 07 01:15:15 PM PDT 24
Peak memory 203688 kb
Host smart-1ae402ea-2587-46cb-b558-89e3b6e40c05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700475580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.700475580
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.771834109
Short name T839
Test name
Test status
Simulation time 1172116874 ps
CPU time 4.1 seconds
Started May 07 01:15:12 PM PDT 24
Finished May 07 01:15:18 PM PDT 24
Peak memory 215544 kb
Host smart-b47c01a0-09d5-42a3-b6be-0142cb13e4f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771834109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp
i_device_same_csr_outstanding.771834109
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.412972982
Short name T847
Test name
Test status
Simulation time 53565400 ps
CPU time 3.1 seconds
Started May 07 01:15:11 PM PDT 24
Finished May 07 01:15:15 PM PDT 24
Peak memory 215680 kb
Host smart-dde0dfff-9eb1-46cb-9dbd-ba15ef2bd885
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412972982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.412972982
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2361412537
Short name T821
Test name
Test status
Simulation time 607516756 ps
CPU time 20.11 seconds
Started May 07 01:15:12 PM PDT 24
Finished May 07 01:15:34 PM PDT 24
Peak memory 215612 kb
Host smart-8608d4ce-6a8a-4f08-bcf6-e86873f15a98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361412537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2361412537
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1596661508
Short name T625
Test name
Test status
Simulation time 37150558 ps
CPU time 0.69 seconds
Started May 07 01:23:08 PM PDT 24
Finished May 07 01:23:10 PM PDT 24
Peak memory 205320 kb
Host smart-f925be4b-0437-414f-b73e-878ed934cf25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596661508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
596661508
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3572421808
Short name T453
Test name
Test status
Simulation time 17239089 ps
CPU time 0.76 seconds
Started May 07 01:23:06 PM PDT 24
Finished May 07 01:23:07 PM PDT 24
Peak memory 205108 kb
Host smart-dd6270e3-4204-4f33-953d-ffea4d847642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572421808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3572421808
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3503692987
Short name T674
Test name
Test status
Simulation time 192938648 ps
CPU time 2.83 seconds
Started May 07 01:23:21 PM PDT 24
Finished May 07 01:23:25 PM PDT 24
Peak memory 222152 kb
Host smart-d20cba7c-f406-49d4-98bd-467b9b057296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503692987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3503692987
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.862215114
Short name T74
Test name
Test status
Simulation time 15309980165 ps
CPU time 11.93 seconds
Started May 07 01:23:01 PM PDT 24
Finished May 07 01:23:14 PM PDT 24
Peak memory 219220 kb
Host smart-2311577b-24d5-4908-952f-fae8e778e69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862215114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
862215114
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2866579724
Short name T644
Test name
Test status
Simulation time 125543413 ps
CPU time 4.21 seconds
Started May 07 01:23:13 PM PDT 24
Finished May 07 01:23:18 PM PDT 24
Peak memory 222640 kb
Host smart-cec7a5cb-0e06-4a9d-91d6-e45028b8e123
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2866579724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2866579724
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.810378894
Short name T51
Test name
Test status
Simulation time 66568662 ps
CPU time 1.07 seconds
Started May 07 01:23:18 PM PDT 24
Finished May 07 01:23:20 PM PDT 24
Peak memory 234824 kb
Host smart-058e780c-9e84-4de2-9321-1d81d13cc28b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810378894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.810378894
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.775579527
Short name T394
Test name
Test status
Simulation time 33911294420 ps
CPU time 40.87 seconds
Started May 07 01:23:14 PM PDT 24
Finished May 07 01:23:56 PM PDT 24
Peak memory 216056 kb
Host smart-d3b368d0-a3ce-4583-b93f-9463d315ce71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775579527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.775579527
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2208481511
Short name T697
Test name
Test status
Simulation time 8762412275 ps
CPU time 23.72 seconds
Started May 07 01:23:07 PM PDT 24
Finished May 07 01:23:32 PM PDT 24
Peak memory 216060 kb
Host smart-3fb3d3a1-a843-476a-b412-b16a566e3824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208481511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2208481511
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.1559114120
Short name T733
Test name
Test status
Simulation time 260198859 ps
CPU time 8.31 seconds
Started May 07 01:23:19 PM PDT 24
Finished May 07 01:23:29 PM PDT 24
Peak memory 216080 kb
Host smart-46c522fc-100a-45ef-ad50-9179d52bead0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559114120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1559114120
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2312111193
Short name T553
Test name
Test status
Simulation time 20536775 ps
CPU time 0.77 seconds
Started May 07 01:23:05 PM PDT 24
Finished May 07 01:23:07 PM PDT 24
Peak memory 205444 kb
Host smart-ee80d1c0-6539-4828-bcb5-2e764abee68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312111193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2312111193
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.970387007
Short name T171
Test name
Test status
Simulation time 7217077233 ps
CPU time 5.87 seconds
Started May 07 01:23:13 PM PDT 24
Finished May 07 01:23:20 PM PDT 24
Peak memory 224272 kb
Host smart-580a992d-d8c5-43fd-afe3-592ff133b31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970387007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.970387007
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3700433831
Short name T545
Test name
Test status
Simulation time 31321884 ps
CPU time 0.71 seconds
Started May 07 01:23:22 PM PDT 24
Finished May 07 01:23:24 PM PDT 24
Peak memory 204984 kb
Host smart-e8e89ecc-37fc-4a64-8574-0fbb63b51f7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700433831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
700433831
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3324865658
Short name T576
Test name
Test status
Simulation time 20929785 ps
CPU time 0.73 seconds
Started May 07 01:23:02 PM PDT 24
Finished May 07 01:23:04 PM PDT 24
Peak memory 206136 kb
Host smart-ea9c3177-d284-4784-8677-7e9fe24fca2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324865658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3324865658
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.4164118719
Short name T654
Test name
Test status
Simulation time 68196086481 ps
CPU time 188.29 seconds
Started May 07 01:23:11 PM PDT 24
Finished May 07 01:26:21 PM PDT 24
Peak memory 233720 kb
Host smart-0638c004-6554-4c85-b712-3fb7b56e5b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164118719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.4164118719
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.588651218
Short name T551
Test name
Test status
Simulation time 25359237 ps
CPU time 1.03 seconds
Started May 07 01:23:02 PM PDT 24
Finished May 07 01:23:05 PM PDT 24
Peak memory 216508 kb
Host smart-e7099b80-9ed5-4ec9-9e66-af970c69ce48
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588651218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.spi_device_mem_parity.588651218
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2927096699
Short name T572
Test name
Test status
Simulation time 4912562780 ps
CPU time 13.16 seconds
Started May 07 01:23:08 PM PDT 24
Finished May 07 01:23:23 PM PDT 24
Peak memory 221704 kb
Host smart-24c6ec33-224d-40e6-8df6-4e8f21e1a3a0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2927096699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2927096699
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3884196370
Short name T54
Test name
Test status
Simulation time 107166273 ps
CPU time 1.24 seconds
Started May 07 01:23:42 PM PDT 24
Finished May 07 01:23:45 PM PDT 24
Peak memory 234868 kb
Host smart-cfeb0668-c209-48aa-a088-bc71058d1e14
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884196370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3884196370
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1070008087
Short name T402
Test name
Test status
Simulation time 2608997772 ps
CPU time 36.83 seconds
Started May 07 01:23:06 PM PDT 24
Finished May 07 01:23:44 PM PDT 24
Peak memory 216352 kb
Host smart-5eca7fa9-f997-4a28-ba9f-0a712fa57db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070008087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1070008087
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2443040023
Short name T481
Test name
Test status
Simulation time 167351236 ps
CPU time 0.8 seconds
Started May 07 01:23:10 PM PDT 24
Finished May 07 01:23:12 PM PDT 24
Peak memory 205432 kb
Host smart-d3793443-26be-4c71-aabd-80a0ec02ac5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443040023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2443040023
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.3872368164
Short name T260
Test name
Test status
Simulation time 2414462274 ps
CPU time 5.64 seconds
Started May 07 01:23:20 PM PDT 24
Finished May 07 01:23:27 PM PDT 24
Peak memory 223080 kb
Host smart-5c7ca9da-8924-47d9-aebe-4e5768456fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872368164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3872368164
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2616734549
Short name T33
Test name
Test status
Simulation time 35826165 ps
CPU time 0.68 seconds
Started May 07 01:23:47 PM PDT 24
Finished May 07 01:23:50 PM PDT 24
Peak memory 204984 kb
Host smart-ee5d2554-c064-4f70-97f8-f993b4adc3ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616734549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2616734549
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3120937170
Short name T329
Test name
Test status
Simulation time 98500908 ps
CPU time 2.71 seconds
Started May 07 01:23:41 PM PDT 24
Finished May 07 01:23:45 PM PDT 24
Peak memory 222208 kb
Host smart-233f892f-6c09-4c75-a566-5fbd1cc15330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120937170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3120937170
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1238872069
Short name T575
Test name
Test status
Simulation time 70641053 ps
CPU time 0.77 seconds
Started May 07 01:23:47 PM PDT 24
Finished May 07 01:23:50 PM PDT 24
Peak memory 206112 kb
Host smart-1b95474a-3ca6-4da5-ab19-4ad00a669f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238872069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1238872069
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1364804993
Short name T369
Test name
Test status
Simulation time 3015497313 ps
CPU time 50.13 seconds
Started May 07 01:23:48 PM PDT 24
Finished May 07 01:24:40 PM PDT 24
Peak memory 257072 kb
Host smart-97a49809-0fa8-4c62-9a9e-6329d8b75109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364804993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1364804993
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3955995434
Short name T178
Test name
Test status
Simulation time 553665849 ps
CPU time 3.66 seconds
Started May 07 01:23:35 PM PDT 24
Finished May 07 01:23:40 PM PDT 24
Peak memory 218436 kb
Host smart-6cd6e8c4-2758-43bd-9bec-656652e940a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955995434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3955995434
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.1934294716
Short name T493
Test name
Test status
Simulation time 59394563 ps
CPU time 1.08 seconds
Started May 07 01:23:49 PM PDT 24
Finished May 07 01:23:52 PM PDT 24
Peak memory 216504 kb
Host smart-9e114deb-0a56-4829-aa8a-0427ce254ff0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934294716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.1934294716
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3282413602
Short name T314
Test name
Test status
Simulation time 5596192497 ps
CPU time 9.68 seconds
Started May 07 01:23:41 PM PDT 24
Finished May 07 01:23:52 PM PDT 24
Peak memory 222380 kb
Host smart-cb5689d9-c11d-4a1f-b4fc-3f6d43de4fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282413602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3282413602
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3947934375
Short name T411
Test name
Test status
Simulation time 3987497242 ps
CPU time 24.86 seconds
Started May 07 01:23:55 PM PDT 24
Finished May 07 01:24:21 PM PDT 24
Peak memory 216232 kb
Host smart-4809459d-5a36-4cc4-b39c-8dc73abbc6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947934375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3947934375
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.842712469
Short name T630
Test name
Test status
Simulation time 9641586277 ps
CPU time 8.06 seconds
Started May 07 01:23:41 PM PDT 24
Finished May 07 01:23:51 PM PDT 24
Peak memory 216040 kb
Host smart-6290b99c-86c6-48da-9796-9a6a8c44ae5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842712469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.842712469
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3479439626
Short name T627
Test name
Test status
Simulation time 254537877 ps
CPU time 3.37 seconds
Started May 07 01:23:44 PM PDT 24
Finished May 07 01:23:48 PM PDT 24
Peak memory 216080 kb
Host smart-2dea1bf0-ae83-4ccc-bdad-5d10979de380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479439626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3479439626
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1069407300
Short name T605
Test name
Test status
Simulation time 224219352 ps
CPU time 0.93 seconds
Started May 07 01:23:40 PM PDT 24
Finished May 07 01:23:42 PM PDT 24
Peak memory 205388 kb
Host smart-84b6ff97-02ec-4fd6-892c-b0ac63d9b2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069407300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1069407300
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.3487998530
Short name T327
Test name
Test status
Simulation time 111390060 ps
CPU time 2.48 seconds
Started May 07 01:23:52 PM PDT 24
Finished May 07 01:23:57 PM PDT 24
Peak memory 222204 kb
Host smart-cddd4512-6a34-4ec7-af6b-b1b5a98fae4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487998530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3487998530
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.4144219228
Short name T534
Test name
Test status
Simulation time 159018814 ps
CPU time 0.68 seconds
Started May 07 01:23:35 PM PDT 24
Finished May 07 01:23:37 PM PDT 24
Peak memory 204356 kb
Host smart-3124963d-df8e-4bd1-8cba-beed01779ed1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144219228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
4144219228
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.984746499
Short name T555
Test name
Test status
Simulation time 34534597 ps
CPU time 0.73 seconds
Started May 07 01:23:33 PM PDT 24
Finished May 07 01:23:35 PM PDT 24
Peak memory 206412 kb
Host smart-542a88ed-b56f-4421-98b6-54a6cb5061f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984746499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.984746499
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2027599040
Short name T597
Test name
Test status
Simulation time 2669694305 ps
CPU time 46.77 seconds
Started May 07 01:23:34 PM PDT 24
Finished May 07 01:24:22 PM PDT 24
Peak memory 248952 kb
Host smart-1eb33b1d-3d9b-4d68-9bd9-804c5192c077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027599040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2027599040
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2138435632
Short name T66
Test name
Test status
Simulation time 411336108 ps
CPU time 4.49 seconds
Started May 07 01:23:40 PM PDT 24
Finished May 07 01:23:47 PM PDT 24
Peak memory 218456 kb
Host smart-99547d7b-6bd9-47cd-ae09-f96ec2da4754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138435632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2138435632
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.2248629022
Short name T38
Test name
Test status
Simulation time 54935632 ps
CPU time 1.04 seconds
Started May 07 01:23:46 PM PDT 24
Finished May 07 01:23:49 PM PDT 24
Peak memory 216476 kb
Host smart-9ba3d372-5b6f-44c0-bd17-faaedad464d1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248629022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.2248629022
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2802280440
Short name T189
Test name
Test status
Simulation time 549859483 ps
CPU time 4.51 seconds
Started May 07 01:23:40 PM PDT 24
Finished May 07 01:23:47 PM PDT 24
Peak memory 221808 kb
Host smart-7d0e0017-1220-482c-918e-0057bd2b68c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802280440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2802280440
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1219612625
Short name T709
Test name
Test status
Simulation time 625550066 ps
CPU time 4.44 seconds
Started May 07 01:23:51 PM PDT 24
Finished May 07 01:23:59 PM PDT 24
Peak memory 222792 kb
Host smart-b7e47be2-d408-4c1f-a9e5-71429c109119
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1219612625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1219612625
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2790398082
Short name T718
Test name
Test status
Simulation time 824004182 ps
CPU time 12.87 seconds
Started May 07 01:23:48 PM PDT 24
Finished May 07 01:24:03 PM PDT 24
Peak memory 216064 kb
Host smart-b8c6f61c-3b67-4b84-b998-abced479ae69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790398082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2790398082
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2168209
Short name T591
Test name
Test status
Simulation time 9112866588 ps
CPU time 7.55 seconds
Started May 07 01:23:41 PM PDT 24
Finished May 07 01:23:50 PM PDT 24
Peak memory 216080 kb
Host smart-5be57dd3-6097-4b60-8f4a-c3dd2ee61642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2168209
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1908767393
Short name T10
Test name
Test status
Simulation time 53650385 ps
CPU time 1.56 seconds
Started May 07 01:23:48 PM PDT 24
Finished May 07 01:23:52 PM PDT 24
Peak memory 216192 kb
Host smart-c1ab31a8-799e-4917-bb92-c42a1b94ce09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908767393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1908767393
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.431804049
Short name T170
Test name
Test status
Simulation time 516363176 ps
CPU time 1.05 seconds
Started May 07 01:23:46 PM PDT 24
Finished May 07 01:23:48 PM PDT 24
Peak memory 206464 kb
Host smart-f14a400d-335a-4fc2-925f-d028d4d6da84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431804049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.431804049
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1188157976
Short name T741
Test name
Test status
Simulation time 51186843 ps
CPU time 0.7 seconds
Started May 07 01:23:46 PM PDT 24
Finished May 07 01:23:48 PM PDT 24
Peak memory 205312 kb
Host smart-401516ce-b88a-4798-bad7-c7d1914cf186
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188157976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1188157976
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2830607168
Short name T691
Test name
Test status
Simulation time 47737340 ps
CPU time 0.7 seconds
Started May 07 01:24:08 PM PDT 24
Finished May 07 01:24:11 PM PDT 24
Peak memory 205804 kb
Host smart-e5fca4de-bca8-4fba-a360-9a90923d4095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830607168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2830607168
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3146045128
Short name T699
Test name
Test status
Simulation time 500949080 ps
CPU time 10.33 seconds
Started May 07 01:23:45 PM PDT 24
Finished May 07 01:23:56 PM PDT 24
Peak memory 224284 kb
Host smart-c6b41489-eb10-495c-92e3-80dac14de82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146045128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3146045128
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.1610664633
Short name T521
Test name
Test status
Simulation time 19009871 ps
CPU time 1.01 seconds
Started May 07 01:23:51 PM PDT 24
Finished May 07 01:23:54 PM PDT 24
Peak memory 216456 kb
Host smart-92765b91-81c1-4465-bfb4-ed2d3c06e3b9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610664633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.1610664633
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.51775790
Short name T725
Test name
Test status
Simulation time 999782972 ps
CPU time 4.22 seconds
Started May 07 01:23:45 PM PDT 24
Finished May 07 01:23:50 PM PDT 24
Peak memory 220360 kb
Host smart-c28a48fc-a3f4-497a-87c0-42c3a23ed200
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=51775790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_direc
t.51775790
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.291345575
Short name T410
Test name
Test status
Simulation time 1155665772 ps
CPU time 14.63 seconds
Started May 07 01:23:38 PM PDT 24
Finished May 07 01:23:54 PM PDT 24
Peak memory 216140 kb
Host smart-8337b676-e40b-48a4-a929-eec1f6fc5923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291345575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.291345575
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2496808413
Short name T611
Test name
Test status
Simulation time 3985598758 ps
CPU time 8.02 seconds
Started May 07 01:23:37 PM PDT 24
Finished May 07 01:23:46 PM PDT 24
Peak memory 216068 kb
Host smart-e63ec88f-30ac-4cb9-9b58-07c4a3586450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496808413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2496808413
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.2637210093
Short name T527
Test name
Test status
Simulation time 284993396 ps
CPU time 2.93 seconds
Started May 07 01:23:32 PM PDT 24
Finished May 07 01:23:42 PM PDT 24
Peak memory 216056 kb
Host smart-de73ff64-4ab5-4f5e-9999-48ac9adeaa9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637210093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2637210093
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.729505215
Short name T613
Test name
Test status
Simulation time 163961993 ps
CPU time 0.73 seconds
Started May 07 01:24:01 PM PDT 24
Finished May 07 01:24:03 PM PDT 24
Peak memory 205444 kb
Host smart-7c1cbd32-2b8b-426b-a6a7-6fc7f3cd94ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729505215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.729505215
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.445786043
Short name T667
Test name
Test status
Simulation time 11441055 ps
CPU time 0.7 seconds
Started May 07 01:23:51 PM PDT 24
Finished May 07 01:23:54 PM PDT 24
Peak memory 204976 kb
Host smart-22ab0229-86d0-4f9a-899f-a7f511fbbff0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445786043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.445786043
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1081711307
Short name T77
Test name
Test status
Simulation time 11498078464 ps
CPU time 64.83 seconds
Started May 07 01:23:50 PM PDT 24
Finished May 07 01:24:57 PM PDT 24
Peak memory 232552 kb
Host smart-6a365657-9693-4dbd-be0a-1236c083d5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081711307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1081711307
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3663050515
Short name T366
Test name
Test status
Simulation time 8020151602 ps
CPU time 32.81 seconds
Started May 07 01:23:48 PM PDT 24
Finished May 07 01:24:23 PM PDT 24
Peak memory 216672 kb
Host smart-7fc9bd25-4d17-4197-a613-d28fd3927ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663050515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3663050515
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.2438348308
Short name T739
Test name
Test status
Simulation time 97787749 ps
CPU time 1.06 seconds
Started May 07 01:23:46 PM PDT 24
Finished May 07 01:23:49 PM PDT 24
Peak memory 217624 kb
Host smart-486c7a0e-ba00-4637-b8f6-9826da7c5144
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438348308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.2438348308
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2480656405
Short name T242
Test name
Test status
Simulation time 30134621935 ps
CPU time 17.88 seconds
Started May 07 01:23:37 PM PDT 24
Finished May 07 01:23:56 PM PDT 24
Peak memory 237336 kb
Host smart-6a4660ed-0bf2-4942-9b57-f0c42b310536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480656405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2480656405
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2677792614
Short name T456
Test name
Test status
Simulation time 4383567872 ps
CPU time 9.94 seconds
Started May 07 01:23:48 PM PDT 24
Finished May 07 01:24:00 PM PDT 24
Peak memory 219920 kb
Host smart-9979e470-b631-4e9e-8c62-54c23b1d3d08
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2677792614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2677792614
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.3117574369
Short name T565
Test name
Test status
Simulation time 165220058 ps
CPU time 0.94 seconds
Started May 07 01:23:50 PM PDT 24
Finished May 07 01:23:54 PM PDT 24
Peak memory 206232 kb
Host smart-f6427d5d-09dc-4531-9a16-8237e1cd44a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117574369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.3117574369
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.194443845
Short name T412
Test name
Test status
Simulation time 1653059301 ps
CPU time 21.79 seconds
Started May 07 01:23:46 PM PDT 24
Finished May 07 01:24:09 PM PDT 24
Peak memory 216036 kb
Host smart-70db777e-839a-48ce-859e-93a18909f53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194443845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.194443845
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3160065164
Short name T436
Test name
Test status
Simulation time 7085436635 ps
CPU time 10.91 seconds
Started May 07 01:23:41 PM PDT 24
Finished May 07 01:23:54 PM PDT 24
Peak memory 216076 kb
Host smart-3a17563b-1326-48e4-82cf-a6f38a1bb72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160065164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3160065164
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3000193572
Short name T58
Test name
Test status
Simulation time 300254914 ps
CPU time 4.4 seconds
Started May 07 01:23:52 PM PDT 24
Finished May 07 01:23:59 PM PDT 24
Peak memory 216040 kb
Host smart-8979def3-4cab-4e6c-bd5b-6e044babe03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000193572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3000193572
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.541354003
Short name T538
Test name
Test status
Simulation time 78936665 ps
CPU time 0.79 seconds
Started May 07 01:23:48 PM PDT 24
Finished May 07 01:23:51 PM PDT 24
Peak memory 205448 kb
Host smart-6a2379e4-d3cc-46f3-b03b-d096c8dc37e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541354003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.541354003
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2767505308
Short name T578
Test name
Test status
Simulation time 17033400 ps
CPU time 0.74 seconds
Started May 07 01:23:48 PM PDT 24
Finished May 07 01:23:50 PM PDT 24
Peak memory 204964 kb
Host smart-216ba757-4737-405b-90cc-310606313771
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767505308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2767505308
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2499499550
Short name T636
Test name
Test status
Simulation time 22014118 ps
CPU time 0.78 seconds
Started May 07 01:23:56 PM PDT 24
Finished May 07 01:23:59 PM PDT 24
Peak memory 206472 kb
Host smart-c9c9b9cc-4992-4944-b0d0-56f238cef3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499499550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2499499550
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2561638289
Short name T688
Test name
Test status
Simulation time 2839637722 ps
CPU time 16.38 seconds
Started May 07 01:23:59 PM PDT 24
Finished May 07 01:24:17 PM PDT 24
Peak memory 240680 kb
Host smart-75a06c25-5780-44cf-a7e4-f255409564f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561638289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2561638289
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1712091479
Short name T207
Test name
Test status
Simulation time 4559150972 ps
CPU time 12.68 seconds
Started May 07 01:23:51 PM PDT 24
Finished May 07 01:24:07 PM PDT 24
Peak memory 219000 kb
Host smart-a953b2f7-7309-4aea-8ea9-32b5ea0fc0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712091479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1712091479
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1357210412
Short name T334
Test name
Test status
Simulation time 2303818105 ps
CPU time 27.28 seconds
Started May 07 01:23:43 PM PDT 24
Finished May 07 01:24:12 PM PDT 24
Peak memory 223688 kb
Host smart-5fe62d01-222c-4b83-8184-0e5b37eaf2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357210412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1357210412
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.2788613126
Short name T577
Test name
Test status
Simulation time 136336521 ps
CPU time 1.03 seconds
Started May 07 01:23:50 PM PDT 24
Finished May 07 01:23:54 PM PDT 24
Peak memory 216348 kb
Host smart-1638682d-738f-4b91-8b88-78b0e37e95d6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788613126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.2788613126
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.828078955
Short name T704
Test name
Test status
Simulation time 5589455099 ps
CPU time 6.28 seconds
Started May 07 01:23:43 PM PDT 24
Finished May 07 01:23:50 PM PDT 24
Peak memory 220332 kb
Host smart-67cdbf8d-365e-449c-a0f4-96083bbfce3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828078955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.828078955
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.996145236
Short name T612
Test name
Test status
Simulation time 628948006 ps
CPU time 4.06 seconds
Started May 07 01:23:46 PM PDT 24
Finished May 07 01:23:51 PM PDT 24
Peak memory 222768 kb
Host smart-14eb5361-cc77-4dfa-81aa-7216e7bd41cb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=996145236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.996145236
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2599412783
Short name T392
Test name
Test status
Simulation time 6227693362 ps
CPU time 7.82 seconds
Started May 07 01:23:45 PM PDT 24
Finished May 07 01:23:54 PM PDT 24
Peak memory 216172 kb
Host smart-4680ec27-12a9-47d9-a4fc-6d6ba101fb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599412783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2599412783
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1663825412
Short name T696
Test name
Test status
Simulation time 89780082026 ps
CPU time 21.71 seconds
Started May 07 01:23:51 PM PDT 24
Finished May 07 01:24:16 PM PDT 24
Peak memory 216092 kb
Host smart-4adba9a8-5138-4dff-bea4-cd583cb9420b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663825412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1663825412
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1005083379
Short name T629
Test name
Test status
Simulation time 83555431 ps
CPU time 1.36 seconds
Started May 07 01:23:49 PM PDT 24
Finished May 07 01:23:54 PM PDT 24
Peak memory 207912 kb
Host smart-61abcd17-f58c-4d41-ad9e-f59870d1e1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005083379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1005083379
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1875748495
Short name T11
Test name
Test status
Simulation time 18957564 ps
CPU time 0.71 seconds
Started May 07 01:23:46 PM PDT 24
Finished May 07 01:23:48 PM PDT 24
Peak memory 205452 kb
Host smart-2a5e6045-08fe-48e5-831b-93993a14fdba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875748495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1875748495
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3893573749
Short name T668
Test name
Test status
Simulation time 13232791 ps
CPU time 0.7 seconds
Started May 07 01:23:46 PM PDT 24
Finished May 07 01:23:48 PM PDT 24
Peak memory 204988 kb
Host smart-dd44b697-b5de-42f6-be0a-a64e8351d644
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893573749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3893573749
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.2241141815
Short name T478
Test name
Test status
Simulation time 24598865 ps
CPU time 0.83 seconds
Started May 07 01:23:40 PM PDT 24
Finished May 07 01:23:42 PM PDT 24
Peak memory 206124 kb
Host smart-1b062096-918f-452d-9a70-ede7320ccbf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241141815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2241141815
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3982803251
Short name T550
Test name
Test status
Simulation time 8280584315 ps
CPU time 101.52 seconds
Started May 07 01:23:48 PM PDT 24
Finished May 07 01:25:32 PM PDT 24
Peak memory 250616 kb
Host smart-18765298-0cc8-4d8e-814d-e7408948845f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982803251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3982803251
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2888603411
Short name T323
Test name
Test status
Simulation time 2781959170 ps
CPU time 26.75 seconds
Started May 07 01:23:49 PM PDT 24
Finished May 07 01:24:18 PM PDT 24
Peak memory 224220 kb
Host smart-72196582-d175-46e0-8a43-17722506347f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888603411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2888603411
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.3051412705
Short name T671
Test name
Test status
Simulation time 68920673 ps
CPU time 1 seconds
Started May 07 01:23:58 PM PDT 24
Finished May 07 01:24:00 PM PDT 24
Peak memory 217644 kb
Host smart-95d25a69-66ac-4436-9c0d-29a819b0b7a2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051412705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.3051412705
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1641526257
Short name T259
Test name
Test status
Simulation time 371626681 ps
CPU time 2.94 seconds
Started May 07 01:23:55 PM PDT 24
Finished May 07 01:24:00 PM PDT 24
Peak memory 222872 kb
Host smart-5d4a750f-f76e-4a4b-bbe5-9c923e78ecc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641526257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1641526257
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1010795359
Short name T579
Test name
Test status
Simulation time 4289128846 ps
CPU time 14.19 seconds
Started May 07 01:23:44 PM PDT 24
Finished May 07 01:23:59 PM PDT 24
Peak memory 222796 kb
Host smart-a842a202-c0bc-4d21-980e-8a054dd1cb1c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1010795359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1010795359
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2861487638
Short name T624
Test name
Test status
Simulation time 675355883 ps
CPU time 3.39 seconds
Started May 07 01:23:48 PM PDT 24
Finished May 07 01:23:54 PM PDT 24
Peak memory 218572 kb
Host smart-d0f32638-397b-4d0e-a237-1cb9f47df753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861487638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2861487638
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3433029363
Short name T689
Test name
Test status
Simulation time 1196600357 ps
CPU time 3.12 seconds
Started May 07 01:23:48 PM PDT 24
Finished May 07 01:23:53 PM PDT 24
Peak memory 216028 kb
Host smart-0fe320e8-a353-4882-ad66-a5a037fc758f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433029363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3433029363
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2645197380
Short name T418
Test name
Test status
Simulation time 183380589 ps
CPU time 2.34 seconds
Started May 07 01:24:00 PM PDT 24
Finished May 07 01:24:04 PM PDT 24
Peak memory 216108 kb
Host smart-ed95ca3b-8542-4717-b95a-bf5f4363894d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645197380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2645197380
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.510507087
Short name T601
Test name
Test status
Simulation time 532040769 ps
CPU time 1.18 seconds
Started May 07 01:23:42 PM PDT 24
Finished May 07 01:23:44 PM PDT 24
Peak memory 206456 kb
Host smart-92cd7e7e-5176-4d90-b27e-22c4edf59532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510507087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.510507087
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.4052390489
Short name T92
Test name
Test status
Simulation time 95389178 ps
CPU time 2.15 seconds
Started May 07 01:23:42 PM PDT 24
Finished May 07 01:23:45 PM PDT 24
Peak memory 216112 kb
Host smart-d9973521-c536-4444-a9e7-4d6b8d62dea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052390489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.4052390489
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3811355895
Short name T561
Test name
Test status
Simulation time 14289260 ps
CPU time 0.68 seconds
Started May 07 01:24:11 PM PDT 24
Finished May 07 01:24:15 PM PDT 24
Peak memory 204948 kb
Host smart-cb01a44f-f049-494a-a54b-03908cab19b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811355895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3811355895
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1641829172
Short name T427
Test name
Test status
Simulation time 16057697 ps
CPU time 0.76 seconds
Started May 07 01:23:52 PM PDT 24
Finished May 07 01:23:55 PM PDT 24
Peak memory 205424 kb
Host smart-a64c7715-ea26-486d-9f36-28c51a168571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641829172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1641829172
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1016668220
Short name T85
Test name
Test status
Simulation time 25227052126 ps
CPU time 39.68 seconds
Started May 07 01:23:48 PM PDT 24
Finished May 07 01:24:30 PM PDT 24
Peak memory 240468 kb
Host smart-63c50b49-d3ce-41d9-be99-e2b61c8e5434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016668220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1016668220
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.1833136139
Short name T185
Test name
Test status
Simulation time 28987922196 ps
CPU time 39.73 seconds
Started May 07 01:23:51 PM PDT 24
Finished May 07 01:24:33 PM PDT 24
Peak memory 229168 kb
Host smart-080b5cfb-9856-457b-9a6f-cb966d8f41a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833136139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1833136139
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.241284838
Short name T595
Test name
Test status
Simulation time 114533697 ps
CPU time 1.06 seconds
Started May 07 01:23:50 PM PDT 24
Finished May 07 01:23:54 PM PDT 24
Peak memory 216576 kb
Host smart-49910b02-510f-41e8-bd5f-59eb8cb6420d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241284838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.spi_device_mem_parity.241284838
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1050211324
Short name T14
Test name
Test status
Simulation time 225937443 ps
CPU time 2.3 seconds
Started May 07 01:23:47 PM PDT 24
Finished May 07 01:23:57 PM PDT 24
Peak memory 215924 kb
Host smart-a27c2f1d-dcdf-489c-b724-4c67030bfe20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050211324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1050211324
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2116486873
Short name T657
Test name
Test status
Simulation time 872416344 ps
CPU time 3.68 seconds
Started May 07 01:23:47 PM PDT 24
Finished May 07 01:23:52 PM PDT 24
Peak memory 222616 kb
Host smart-3ef456ae-7a07-44fa-be9a-48923a60c5c0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2116486873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2116486873
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1241634945
Short name T408
Test name
Test status
Simulation time 541458538 ps
CPU time 3.36 seconds
Started May 07 01:23:50 PM PDT 24
Finished May 07 01:23:56 PM PDT 24
Peak memory 216144 kb
Host smart-bf83ba84-747e-4e1b-84af-5f50269ff23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241634945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1241634945
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3004549667
Short name T492
Test name
Test status
Simulation time 10468173597 ps
CPU time 8.88 seconds
Started May 07 01:23:45 PM PDT 24
Finished May 07 01:23:55 PM PDT 24
Peak memory 216112 kb
Host smart-5cd78d1e-883f-449c-b561-dbba6fac8e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004549667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3004549667
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.4242530441
Short name T17
Test name
Test status
Simulation time 254356675 ps
CPU time 2.42 seconds
Started May 07 01:23:43 PM PDT 24
Finished May 07 01:23:47 PM PDT 24
Peak memory 216080 kb
Host smart-eb1a566b-7e87-4420-b02c-77f31b777409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242530441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.4242530441
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.113307327
Short name T439
Test name
Test status
Simulation time 422805632 ps
CPU time 1.04 seconds
Started May 07 01:23:50 PM PDT 24
Finished May 07 01:23:54 PM PDT 24
Peak memory 206564 kb
Host smart-184f5d5a-befe-4b2c-9473-f6e9daa57016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113307327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.113307327
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1599413485
Short name T569
Test name
Test status
Simulation time 14173314 ps
CPU time 0.68 seconds
Started May 07 01:23:49 PM PDT 24
Finished May 07 01:23:52 PM PDT 24
Peak memory 204988 kb
Host smart-619fe962-d300-45a5-b18e-7df4c733fbbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599413485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1599413485
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2236743006
Short name T432
Test name
Test status
Simulation time 13636714 ps
CPU time 0.74 seconds
Started May 07 01:24:08 PM PDT 24
Finished May 07 01:24:12 PM PDT 24
Peak memory 205128 kb
Host smart-22ea0190-66e2-490a-8556-0d654e9de130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236743006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2236743006
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_intercept.4203080635
Short name T309
Test name
Test status
Simulation time 36495997516 ps
CPU time 37.98 seconds
Started May 07 01:23:58 PM PDT 24
Finished May 07 01:24:37 PM PDT 24
Peak memory 216396 kb
Host smart-df9621c4-3e86-4228-8bc3-0625332771d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203080635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.4203080635
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2356759265
Short name T695
Test name
Test status
Simulation time 1104985395 ps
CPU time 11.91 seconds
Started May 07 01:23:58 PM PDT 24
Finished May 07 01:24:12 PM PDT 24
Peak memory 223048 kb
Host smart-d1393758-c808-4152-af75-902e210095b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356759265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2356759265
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.900445800
Short name T167
Test name
Test status
Simulation time 57636102 ps
CPU time 1.06 seconds
Started May 07 01:23:50 PM PDT 24
Finished May 07 01:23:54 PM PDT 24
Peak memory 216484 kb
Host smart-7272e745-0b1e-4793-8f8d-1510f62cd9fd
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900445800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.spi_device_mem_parity.900445800
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3037626069
Short name T666
Test name
Test status
Simulation time 1577003146 ps
CPU time 3.27 seconds
Started May 07 01:23:59 PM PDT 24
Finished May 07 01:24:04 PM PDT 24
Peak memory 220264 kb
Host smart-2fbcc6ca-0715-4cee-9752-40abcde85c58
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3037626069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3037626069
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.182693614
Short name T680
Test name
Test status
Simulation time 4487668652 ps
CPU time 9 seconds
Started May 07 01:23:53 PM PDT 24
Finished May 07 01:24:04 PM PDT 24
Peak memory 216064 kb
Host smart-28cdf4b7-6459-4596-afd1-a877b358f18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182693614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.182693614
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.508662632
Short name T524
Test name
Test status
Simulation time 68517581 ps
CPU time 0.86 seconds
Started May 07 01:24:09 PM PDT 24
Finished May 07 01:24:12 PM PDT 24
Peak memory 205920 kb
Host smart-e660a016-d10c-4229-b37c-5dae2befc64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508662632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.508662632
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3582005726
Short name T173
Test name
Test status
Simulation time 19661612 ps
CPU time 0.72 seconds
Started May 07 01:24:05 PM PDT 24
Finished May 07 01:24:07 PM PDT 24
Peak memory 205396 kb
Host smart-1b0184a8-1003-4c2d-8474-690677e1c401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582005726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3582005726
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3739174684
Short name T208
Test name
Test status
Simulation time 14482088608 ps
CPU time 22.06 seconds
Started May 07 01:23:58 PM PDT 24
Finished May 07 01:24:22 PM PDT 24
Peak memory 224556 kb
Host smart-08ed96ba-a109-4324-b3fe-5e8d7c40ab67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739174684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3739174684
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3972303431
Short name T734
Test name
Test status
Simulation time 69851751 ps
CPU time 0.78 seconds
Started May 07 01:24:03 PM PDT 24
Finished May 07 01:24:05 PM PDT 24
Peak memory 205092 kb
Host smart-10f2ade2-f144-4ea8-a1e6-73dabd68bab5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972303431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3972303431
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2101121836
Short name T651
Test name
Test status
Simulation time 16207945 ps
CPU time 0.77 seconds
Started May 07 01:24:10 PM PDT 24
Finished May 07 01:24:14 PM PDT 24
Peak memory 206412 kb
Host smart-9d072edd-ed8b-4187-b67f-c5418e25300c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101121836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2101121836
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3075622699
Short name T669
Test name
Test status
Simulation time 749893206 ps
CPU time 7.59 seconds
Started May 07 01:23:52 PM PDT 24
Finished May 07 01:24:02 PM PDT 24
Peak memory 240668 kb
Host smart-d4174738-ce4f-432b-b32b-4d23041c8dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075622699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3075622699
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.145800613
Short name T196
Test name
Test status
Simulation time 1964276728 ps
CPU time 14.61 seconds
Started May 07 01:23:49 PM PDT 24
Finished May 07 01:24:06 PM PDT 24
Peak memory 239476 kb
Host smart-ce2550a4-1029-437b-b9cb-a8046d0dddd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145800613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.145800613
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.2669166589
Short name T621
Test name
Test status
Simulation time 41322178 ps
CPU time 1.02 seconds
Started May 07 01:23:53 PM PDT 24
Finished May 07 01:23:56 PM PDT 24
Peak memory 216500 kb
Host smart-bd193676-2215-4060-b395-33932d507569
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669166589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.2669166589
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3549869543
Short name T286
Test name
Test status
Simulation time 5011645691 ps
CPU time 15.68 seconds
Started May 07 01:23:50 PM PDT 24
Finished May 07 01:24:08 PM PDT 24
Peak memory 218936 kb
Host smart-2e558a39-bcb1-4f14-be1e-63d50549a85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549869543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3549869543
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2456330410
Short name T89
Test name
Test status
Simulation time 604244499 ps
CPU time 5.4 seconds
Started May 07 01:24:08 PM PDT 24
Finished May 07 01:24:16 PM PDT 24
Peak memory 238832 kb
Host smart-3a2f8368-fcc1-4dd0-bbef-1a7b5a761bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456330410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2456330410
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3215048489
Short name T698
Test name
Test status
Simulation time 2912221073 ps
CPU time 8.27 seconds
Started May 07 01:23:57 PM PDT 24
Finished May 07 01:24:06 PM PDT 24
Peak memory 218616 kb
Host smart-b24590bb-5ad7-41f4-a70a-791fa89ae0ff
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3215048489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3215048489
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1716302119
Short name T421
Test name
Test status
Simulation time 9106979270 ps
CPU time 43.9 seconds
Started May 07 01:24:09 PM PDT 24
Finished May 07 01:24:55 PM PDT 24
Peak memory 216168 kb
Host smart-c3610049-d920-45dc-90f8-42627b1c55bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716302119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1716302119
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3595412378
Short name T469
Test name
Test status
Simulation time 1051653954 ps
CPU time 6.74 seconds
Started May 07 01:23:53 PM PDT 24
Finished May 07 01:24:02 PM PDT 24
Peak memory 215972 kb
Host smart-3466af3f-2029-4c70-ac99-963ba55ec627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595412378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3595412378
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1300188917
Short name T59
Test name
Test status
Simulation time 704883422 ps
CPU time 4.69 seconds
Started May 07 01:23:50 PM PDT 24
Finished May 07 01:23:57 PM PDT 24
Peak memory 216124 kb
Host smart-42e78440-eb18-4b18-b16b-93769f30e513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300188917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1300188917
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1008345763
Short name T539
Test name
Test status
Simulation time 103814806 ps
CPU time 0.82 seconds
Started May 07 01:23:49 PM PDT 24
Finished May 07 01:23:52 PM PDT 24
Peak memory 205432 kb
Host smart-8a9d4465-8bfa-49ec-a2e5-078b36ecc27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008345763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1008345763
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3448653784
Short name T658
Test name
Test status
Simulation time 53472174 ps
CPU time 0.83 seconds
Started May 07 01:23:49 PM PDT 24
Finished May 07 01:23:53 PM PDT 24
Peak memory 206120 kb
Host smart-7238baa8-e8b1-4249-9cca-275bf8475fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448653784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3448653784
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.991677972
Short name T635
Test name
Test status
Simulation time 2226170421 ps
CPU time 36.02 seconds
Started May 07 01:23:49 PM PDT 24
Finished May 07 01:24:28 PM PDT 24
Peak memory 248964 kb
Host smart-e412fda8-d644-4858-8cbb-ed435c8b55fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991677972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.991677972
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.2405449480
Short name T655
Test name
Test status
Simulation time 658311711 ps
CPU time 8.09 seconds
Started May 07 01:24:12 PM PDT 24
Finished May 07 01:24:23 PM PDT 24
Peak memory 223840 kb
Host smart-3a6e7ae5-67c2-44e2-b977-90c69afe64f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405449480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2405449480
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.3928456673
Short name T646
Test name
Test status
Simulation time 44818639 ps
CPU time 0.98 seconds
Started May 07 01:23:49 PM PDT 24
Finished May 07 01:23:52 PM PDT 24
Peak memory 216420 kb
Host smart-163f1cbd-ee57-4738-a62a-93eef1e4fb9a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928456673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.3928456673
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1817790020
Short name T266
Test name
Test status
Simulation time 2041838391 ps
CPU time 7.83 seconds
Started May 07 01:24:05 PM PDT 24
Finished May 07 01:24:15 PM PDT 24
Peak memory 223944 kb
Host smart-d7ae180d-fade-436f-8b86-3d593c98d3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817790020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1817790020
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1636100615
Short name T637
Test name
Test status
Simulation time 422121057 ps
CPU time 6.85 seconds
Started May 07 01:23:50 PM PDT 24
Finished May 07 01:24:00 PM PDT 24
Peak memory 221416 kb
Host smart-bc00870a-4a91-439b-ba70-eed1acdb803a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1636100615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1636100615
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1694689971
Short name T466
Test name
Test status
Simulation time 41748161410 ps
CPU time 22.56 seconds
Started May 07 01:23:48 PM PDT 24
Finished May 07 01:24:13 PM PDT 24
Peak memory 216036 kb
Host smart-bf41237e-2828-4def-b65a-67738bc7be5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694689971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1694689971
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3509140878
Short name T571
Test name
Test status
Simulation time 18433266 ps
CPU time 0.93 seconds
Started May 07 01:24:11 PM PDT 24
Finished May 07 01:24:15 PM PDT 24
Peak memory 206796 kb
Host smart-4b3bc07a-204f-495a-8784-13fa6392b367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509140878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3509140878
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3288123529
Short name T491
Test name
Test status
Simulation time 141787615 ps
CPU time 0.82 seconds
Started May 07 01:23:53 PM PDT 24
Finished May 07 01:23:56 PM PDT 24
Peak memory 205444 kb
Host smart-9c739b71-4de4-4580-818c-c28a5ce19d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288123529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3288123529
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.4220433395
Short name T465
Test name
Test status
Simulation time 18525851 ps
CPU time 0.76 seconds
Started May 07 01:23:26 PM PDT 24
Finished May 07 01:23:28 PM PDT 24
Peak memory 205280 kb
Host smart-a02c606d-107a-47da-9fb6-c3d52fe2ebf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220433395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.4
220433395
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.699608339
Short name T23
Test name
Test status
Simulation time 15658892 ps
CPU time 0.83 seconds
Started May 07 01:23:18 PM PDT 24
Finished May 07 01:23:19 PM PDT 24
Peak memory 206356 kb
Host smart-9473e1f7-64ba-4cdf-9d1b-775402e472f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699608339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.699608339
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.4022940793
Short name T641
Test name
Test status
Simulation time 930403187 ps
CPU time 20.51 seconds
Started May 07 01:23:19 PM PDT 24
Finished May 07 01:23:40 PM PDT 24
Peak memory 232516 kb
Host smart-bcf58f73-d479-487d-ad2d-013f43a28d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022940793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.4022940793
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3789547422
Short name T462
Test name
Test status
Simulation time 145298476 ps
CPU time 3.1 seconds
Started May 07 01:23:08 PM PDT 24
Finished May 07 01:23:12 PM PDT 24
Peak memory 216488 kb
Host smart-67b2db3f-7983-4bfa-a214-998b8c73558b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789547422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3789547422
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.578282156
Short name T720
Test name
Test status
Simulation time 123448420 ps
CPU time 1.12 seconds
Started May 07 01:23:21 PM PDT 24
Finished May 07 01:23:23 PM PDT 24
Peak memory 216488 kb
Host smart-70972ab9-ca11-42f3-a8c7-5e06edd891ad
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578282156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.spi_device_mem_parity.578282156
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.284745508
Short name T234
Test name
Test status
Simulation time 10109254458 ps
CPU time 12.2 seconds
Started May 07 01:23:21 PM PDT 24
Finished May 07 01:23:35 PM PDT 24
Peak memory 222008 kb
Host smart-54c2be71-3cdf-4da5-85b8-810eaaafb2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284745508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.284745508
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2576431095
Short name T711
Test name
Test status
Simulation time 1659580099 ps
CPU time 4.21 seconds
Started May 07 01:23:18 PM PDT 24
Finished May 07 01:23:23 PM PDT 24
Peak memory 218940 kb
Host smart-8f8273df-7dfd-48b8-ba37-4c100d70d5ba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2576431095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2576431095
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3090650078
Short name T52
Test name
Test status
Simulation time 113755311 ps
CPU time 1.1 seconds
Started May 07 01:23:02 PM PDT 24
Finished May 07 01:23:05 PM PDT 24
Peak memory 234812 kb
Host smart-16ad3d35-a3cb-45f5-853e-e69a95214f20
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090650078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3090650078
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2477979134
Short name T44
Test name
Test status
Simulation time 156267741 ps
CPU time 1.02 seconds
Started May 07 01:23:21 PM PDT 24
Finished May 07 01:23:23 PM PDT 24
Peak memory 206412 kb
Host smart-a0833763-3d08-44cd-be99-ccf2105bb26a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477979134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2477979134
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.2387725333
Short name T401
Test name
Test status
Simulation time 35807166230 ps
CPU time 47.68 seconds
Started May 07 01:23:21 PM PDT 24
Finished May 07 01:24:10 PM PDT 24
Peak memory 216276 kb
Host smart-c9ea74d7-79d8-4360-99b1-e608d89c79e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387725333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2387725333
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.106326552
Short name T500
Test name
Test status
Simulation time 2448785251 ps
CPU time 11.66 seconds
Started May 07 01:23:26 PM PDT 24
Finished May 07 01:23:38 PM PDT 24
Peak memory 216056 kb
Host smart-97070923-61e4-42b1-a8e6-951acbf40947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106326552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.106326552
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3344806383
Short name T532
Test name
Test status
Simulation time 933252955 ps
CPU time 2.35 seconds
Started May 07 01:23:29 PM PDT 24
Finished May 07 01:23:32 PM PDT 24
Peak memory 216068 kb
Host smart-07cdee75-9586-4817-adb2-671919ad7373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344806383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3344806383
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.87440515
Short name T742
Test name
Test status
Simulation time 157404213 ps
CPU time 0.88 seconds
Started May 07 01:23:19 PM PDT 24
Finished May 07 01:23:21 PM PDT 24
Peak memory 205424 kb
Host smart-b1e49283-13a1-437b-b201-cfab2e60f76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87440515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.87440515
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3656785879
Short name T288
Test name
Test status
Simulation time 511380369 ps
CPU time 8 seconds
Started May 07 01:23:19 PM PDT 24
Finished May 07 01:23:29 PM PDT 24
Peak memory 224272 kb
Host smart-97b46c95-6d5e-4271-8b8a-b1320c4aa250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656785879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3656785879
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1448690265
Short name T540
Test name
Test status
Simulation time 42084688 ps
CPU time 0.76 seconds
Started May 07 01:23:49 PM PDT 24
Finished May 07 01:23:52 PM PDT 24
Peak memory 204128 kb
Host smart-df8d89ce-aea7-468d-83b0-7240eb55e99f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448690265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1448690265
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1929534574
Short name T326
Test name
Test status
Simulation time 647986391 ps
CPU time 4.81 seconds
Started May 07 01:23:53 PM PDT 24
Finished May 07 01:24:00 PM PDT 24
Peak memory 222708 kb
Host smart-84aa8f6f-b593-48fb-b976-72813760b8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929534574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1929534574
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.260090123
Short name T20
Test name
Test status
Simulation time 45336727 ps
CPU time 0.8 seconds
Started May 07 01:24:02 PM PDT 24
Finished May 07 01:24:05 PM PDT 24
Peak memory 206452 kb
Host smart-4125bdc6-aebf-4e30-b505-41e38f78a301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260090123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.260090123
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_intercept.753451516
Short name T291
Test name
Test status
Simulation time 990443615 ps
CPU time 12.8 seconds
Started May 07 01:23:57 PM PDT 24
Finished May 07 01:24:11 PM PDT 24
Peak memory 218548 kb
Host smart-17b938a6-919c-4b22-98e2-a115cc642f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753451516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.753451516
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.4033323652
Short name T499
Test name
Test status
Simulation time 281092660 ps
CPU time 3.97 seconds
Started May 07 01:23:53 PM PDT 24
Finished May 07 01:23:59 PM PDT 24
Peak memory 222728 kb
Host smart-5eba8b3e-b1d1-4493-bfe1-83e56737e63a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4033323652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.4033323652
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.703005943
Short name T19
Test name
Test status
Simulation time 32357806179 ps
CPU time 13.25 seconds
Started May 07 01:23:49 PM PDT 24
Finished May 07 01:24:05 PM PDT 24
Peak memory 216044 kb
Host smart-5df1a121-da18-42e4-9370-3b7c213240c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703005943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.703005943
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.259129000
Short name T700
Test name
Test status
Simulation time 80366166 ps
CPU time 1.65 seconds
Started May 07 01:23:53 PM PDT 24
Finished May 07 01:23:57 PM PDT 24
Peak memory 207972 kb
Host smart-650b06f6-966d-4d16-b5ab-1e65386db3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259129000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.259129000
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3965087686
Short name T470
Test name
Test status
Simulation time 65132879 ps
CPU time 0.78 seconds
Started May 07 01:23:55 PM PDT 24
Finished May 07 01:23:57 PM PDT 24
Peak memory 205444 kb
Host smart-5d942679-6ac6-4c58-8c9d-75ca99e25639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965087686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3965087686
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.2923023272
Short name T252
Test name
Test status
Simulation time 2563484545 ps
CPU time 14.14 seconds
Started May 07 01:24:13 PM PDT 24
Finished May 07 01:24:30 PM PDT 24
Peak memory 236268 kb
Host smart-0c4fbd38-e035-444b-9541-523af1b22740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923023272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2923023272
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1976035369
Short name T450
Test name
Test status
Simulation time 25329290 ps
CPU time 0.72 seconds
Started May 07 01:24:06 PM PDT 24
Finished May 07 01:24:09 PM PDT 24
Peak memory 204368 kb
Host smart-cae9960a-719a-4769-95e8-6b511b78c98c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976035369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1976035369
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.1339510129
Short name T645
Test name
Test status
Simulation time 180110725 ps
CPU time 0.78 seconds
Started May 07 01:24:08 PM PDT 24
Finished May 07 01:24:12 PM PDT 24
Peak memory 205408 kb
Host smart-165760c9-f774-4543-86b7-adb71b71d773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339510129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1339510129
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_intercept.3092806424
Short name T633
Test name
Test status
Simulation time 3995509552 ps
CPU time 11.23 seconds
Started May 07 01:24:27 PM PDT 24
Finished May 07 01:24:40 PM PDT 24
Peak memory 223616 kb
Host smart-ff04f174-fbec-4bc4-9446-d0496daf4486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092806424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3092806424
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3298601600
Short name T333
Test name
Test status
Simulation time 396198990 ps
CPU time 3.84 seconds
Started May 07 01:24:08 PM PDT 24
Finished May 07 01:24:15 PM PDT 24
Peak memory 222168 kb
Host smart-ed29643e-5ee9-4565-ab88-2164773af73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298601600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3298601600
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2590563534
Short name T68
Test name
Test status
Simulation time 484184017 ps
CPU time 3.4 seconds
Started May 07 01:23:57 PM PDT 24
Finished May 07 01:24:02 PM PDT 24
Peak memory 222052 kb
Host smart-17a93f0a-31ce-4a1b-8b92-3ad92afe88ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590563534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2590563534
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.4122599110
Short name T542
Test name
Test status
Simulation time 692583383 ps
CPU time 11.36 seconds
Started May 07 01:24:09 PM PDT 24
Finished May 07 01:24:23 PM PDT 24
Peak memory 219784 kb
Host smart-d38f7aac-99dd-44a3-99b0-8814c1c1b75f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4122599110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.4122599110
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.4182808034
Short name T100
Test name
Test status
Simulation time 13922307338 ps
CPU time 21.47 seconds
Started May 07 01:24:03 PM PDT 24
Finished May 07 01:24:26 PM PDT 24
Peak memory 216152 kb
Host smart-db98cdfe-152a-4f3a-a22f-e4f6741baceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182808034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.4182808034
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3151512996
Short name T487
Test name
Test status
Simulation time 2087348992 ps
CPU time 3.36 seconds
Started May 07 01:24:15 PM PDT 24
Finished May 07 01:24:21 PM PDT 24
Peak memory 215976 kb
Host smart-cf75d659-f522-4ab0-8447-a28162eda5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151512996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3151512996
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1791582602
Short name T506
Test name
Test status
Simulation time 343142281 ps
CPU time 0.99 seconds
Started May 07 01:24:01 PM PDT 24
Finished May 07 01:24:03 PM PDT 24
Peak memory 206436 kb
Host smart-7251135d-6688-4db0-96b2-e9f48a2a8f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791582602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1791582602
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2437102187
Short name T3
Test name
Test status
Simulation time 52836821 ps
CPU time 0.84 seconds
Started May 07 01:24:04 PM PDT 24
Finished May 07 01:24:07 PM PDT 24
Peak memory 205460 kb
Host smart-dfe79bcc-8a97-4b4c-bc4f-8448916a6518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437102187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2437102187
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3208672168
Short name T7
Test name
Test status
Simulation time 2196607993 ps
CPU time 5.77 seconds
Started May 07 01:23:52 PM PDT 24
Finished May 07 01:24:00 PM PDT 24
Peak memory 221172 kb
Host smart-0ef8df55-f80c-4d30-9afd-00e3a9f93466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208672168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3208672168
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.300345810
Short name T708
Test name
Test status
Simulation time 31692985 ps
CPU time 0.68 seconds
Started May 07 01:24:02 PM PDT 24
Finished May 07 01:24:04 PM PDT 24
Peak memory 204952 kb
Host smart-aea4b480-0c45-412c-96c6-ea25363d1f7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300345810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.300345810
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2736956391
Short name T537
Test name
Test status
Simulation time 912576867 ps
CPU time 6.78 seconds
Started May 07 01:24:11 PM PDT 24
Finished May 07 01:24:20 PM PDT 24
Peak memory 233420 kb
Host smart-87ca3654-a95a-456a-95a7-ef06fee3108a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736956391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2736956391
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1026899199
Short name T24
Test name
Test status
Simulation time 17340345 ps
CPU time 0.76 seconds
Started May 07 01:24:09 PM PDT 24
Finished May 07 01:24:12 PM PDT 24
Peak memory 205416 kb
Host smart-7ba74369-de55-40b3-a5b0-561d1778d2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026899199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1026899199
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.257008312
Short name T546
Test name
Test status
Simulation time 48018231704 ps
CPU time 158.31 seconds
Started May 07 01:24:06 PM PDT 24
Finished May 07 01:26:46 PM PDT 24
Peak memory 257132 kb
Host smart-00f5427a-5878-49c9-90b6-40f3cb7324c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257008312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.257008312
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.3566464645
Short name T355
Test name
Test status
Simulation time 5531548910 ps
CPU time 14.14 seconds
Started May 07 01:24:10 PM PDT 24
Finished May 07 01:24:27 PM PDT 24
Peak memory 224344 kb
Host smart-2cb281bd-4851-48e9-a810-d5912fc22d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566464645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3566464645
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1002934489
Short name T663
Test name
Test status
Simulation time 1002469690 ps
CPU time 13.59 seconds
Started May 07 01:23:53 PM PDT 24
Finished May 07 01:24:09 PM PDT 24
Peak memory 219068 kb
Host smart-b0f4f704-c2cb-440b-9339-678475f31df2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1002934489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1002934489
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3921474595
Short name T451
Test name
Test status
Simulation time 140202823 ps
CPU time 0.93 seconds
Started May 07 01:24:17 PM PDT 24
Finished May 07 01:24:20 PM PDT 24
Peak memory 206460 kb
Host smart-23e6675e-5a9a-4d67-9ce0-228b547ad981
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921474595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3921474595
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2282673203
Short name T97
Test name
Test status
Simulation time 998684425 ps
CPU time 6.92 seconds
Started May 07 01:24:13 PM PDT 24
Finished May 07 01:24:23 PM PDT 24
Peak memory 216100 kb
Host smart-676e3451-610d-4fc4-b934-677f98c5804d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282673203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2282673203
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2361059879
Short name T568
Test name
Test status
Simulation time 1385150617 ps
CPU time 3.98 seconds
Started May 07 01:24:09 PM PDT 24
Finished May 07 01:24:16 PM PDT 24
Peak memory 215888 kb
Host smart-1e998bc8-661c-4e96-89c8-c69e9c566c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361059879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2361059879
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3568997048
Short name T468
Test name
Test status
Simulation time 110441060 ps
CPU time 2.33 seconds
Started May 07 01:23:59 PM PDT 24
Finished May 07 01:24:04 PM PDT 24
Peak memory 216056 kb
Host smart-63fa1c9c-560f-4f0d-b0ad-a0a480e4d29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568997048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3568997048
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.33303322
Short name T590
Test name
Test status
Simulation time 417756183 ps
CPU time 1.01 seconds
Started May 07 01:24:09 PM PDT 24
Finished May 07 01:24:13 PM PDT 24
Peak memory 206428 kb
Host smart-cacb8676-2c55-44f4-90af-6bd04fca1d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33303322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.33303322
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1776904940
Short name T332
Test name
Test status
Simulation time 466410828 ps
CPU time 3.07 seconds
Started May 07 01:24:12 PM PDT 24
Finished May 07 01:24:18 PM PDT 24
Peak memory 216408 kb
Host smart-940c175f-55c2-42c4-a959-89baf2471aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776904940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1776904940
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3238842670
Short name T496
Test name
Test status
Simulation time 14250326 ps
CPU time 0.73 seconds
Started May 07 01:23:59 PM PDT 24
Finished May 07 01:24:01 PM PDT 24
Peak memory 204996 kb
Host smart-566fa8b2-20da-4c13-a6bf-103dcef31eed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238842670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3238842670
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1386506650
Short name T656
Test name
Test status
Simulation time 39818874 ps
CPU time 0.87 seconds
Started May 07 01:24:06 PM PDT 24
Finished May 07 01:24:09 PM PDT 24
Peak memory 206088 kb
Host smart-1eab0d12-a61a-4963-8445-bbcb1c3b8edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386506650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1386506650
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3862867826
Short name T158
Test name
Test status
Simulation time 821466155 ps
CPU time 19.1 seconds
Started May 07 01:24:21 PM PDT 24
Finished May 07 01:24:41 PM PDT 24
Peak memory 240392 kb
Host smart-93ebaa82-2f92-4ecd-aa01-2a46aab2f525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862867826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3862867826
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.316486897
Short name T269
Test name
Test status
Simulation time 20701207270 ps
CPU time 49.31 seconds
Started May 07 01:24:20 PM PDT 24
Finished May 07 01:25:11 PM PDT 24
Peak memory 232592 kb
Host smart-2d8b08db-44e3-407d-a8f8-a61559c1f55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316486897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.316486897
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2302303173
Short name T215
Test name
Test status
Simulation time 2718650436 ps
CPU time 33.76 seconds
Started May 07 01:23:55 PM PDT 24
Finished May 07 01:24:31 PM PDT 24
Peak memory 223288 kb
Host smart-5b248ac7-ab6d-446e-8897-ab1fc76d1091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302303173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2302303173
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3082944257
Short name T8
Test name
Test status
Simulation time 2006336211 ps
CPU time 8.68 seconds
Started May 07 01:23:56 PM PDT 24
Finished May 07 01:24:06 PM PDT 24
Peak memory 216680 kb
Host smart-6ef43d1f-91bf-4b75-8f1e-a6d88c73e1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082944257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3082944257
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.1790182330
Short name T508
Test name
Test status
Simulation time 1283623213 ps
CPU time 3.44 seconds
Started May 07 01:24:10 PM PDT 24
Finished May 07 01:24:17 PM PDT 24
Peak memory 222756 kb
Host smart-d6ac5106-91da-44be-8de6-9fb1fa0aead1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1790182330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.1790182330
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1878996701
Short name T373
Test name
Test status
Simulation time 177932180 ps
CPU time 0.94 seconds
Started May 07 01:24:12 PM PDT 24
Finished May 07 01:24:16 PM PDT 24
Peak memory 206548 kb
Host smart-53ec0f15-7b42-44f5-af3b-f76b4a573bcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878996701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1878996701
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3203631556
Short name T407
Test name
Test status
Simulation time 853324256 ps
CPU time 7.04 seconds
Started May 07 01:23:54 PM PDT 24
Finished May 07 01:24:03 PM PDT 24
Peak memory 216104 kb
Host smart-faae0e1b-e571-4e07-a152-115a24ff49fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203631556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3203631556
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3552655878
Short name T515
Test name
Test status
Simulation time 2776804440 ps
CPU time 13.87 seconds
Started May 07 01:24:15 PM PDT 24
Finished May 07 01:24:31 PM PDT 24
Peak memory 216048 kb
Host smart-4cf694ff-5d74-4d6a-9ed0-755e48d58534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552655878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3552655878
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2418963552
Short name T405
Test name
Test status
Simulation time 945773009 ps
CPU time 3.3 seconds
Started May 07 01:24:01 PM PDT 24
Finished May 07 01:24:06 PM PDT 24
Peak memory 216068 kb
Host smart-29bd510e-ff67-44f3-860e-40c112838014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418963552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2418963552
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1302514550
Short name T507
Test name
Test status
Simulation time 108422165 ps
CPU time 0.84 seconds
Started May 07 01:24:01 PM PDT 24
Finished May 07 01:24:04 PM PDT 24
Peak memory 205448 kb
Host smart-6d3b1a41-06e4-47b3-ab7a-8027ba6f4a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302514550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1302514550
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3820918142
Short name T596
Test name
Test status
Simulation time 22723529 ps
CPU time 0.73 seconds
Started May 07 01:24:03 PM PDT 24
Finished May 07 01:24:06 PM PDT 24
Peak memory 204340 kb
Host smart-c10bbe26-6866-438d-b583-10ff2436e279
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820918142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3820918142
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1740845999
Short name T677
Test name
Test status
Simulation time 37500298 ps
CPU time 0.8 seconds
Started May 07 01:24:00 PM PDT 24
Finished May 07 01:24:03 PM PDT 24
Peak memory 206076 kb
Host smart-28bc2070-adfd-4fc5-bb5a-d57d886ac836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740845999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1740845999
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2458611233
Short name T472
Test name
Test status
Simulation time 9855658188 ps
CPU time 57.99 seconds
Started May 07 01:24:07 PM PDT 24
Finished May 07 01:25:08 PM PDT 24
Peak memory 238540 kb
Host smart-7ed5bad5-8b1e-40c0-930e-a1f18c73fb29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458611233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2458611233
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3978217400
Short name T114
Test name
Test status
Simulation time 546389607 ps
CPU time 5.01 seconds
Started May 07 01:24:18 PM PDT 24
Finished May 07 01:24:25 PM PDT 24
Peak memory 217084 kb
Host smart-6b9103fe-a1b8-4db3-b31b-3172960302ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978217400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3978217400
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3734888289
Short name T471
Test name
Test status
Simulation time 1487722054 ps
CPU time 12.36 seconds
Started May 07 01:24:10 PM PDT 24
Finished May 07 01:24:26 PM PDT 24
Peak memory 218992 kb
Host smart-6994437d-c8fe-453c-b882-b1bc04fe9995
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3734888289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3734888289
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2527394585
Short name T393
Test name
Test status
Simulation time 13512900282 ps
CPU time 33.57 seconds
Started May 07 01:23:57 PM PDT 24
Finished May 07 01:24:32 PM PDT 24
Peak memory 216120 kb
Host smart-14b69144-2e69-4604-acce-d6446daaeaa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527394585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2527394585
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.4090905720
Short name T563
Test name
Test status
Simulation time 7697427344 ps
CPU time 10.03 seconds
Started May 07 01:24:09 PM PDT 24
Finished May 07 01:24:22 PM PDT 24
Peak memory 216088 kb
Host smart-f0f9954e-ee2d-40d1-8f8f-4a963cb376a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090905720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.4090905720
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2495035770
Short name T614
Test name
Test status
Simulation time 33535261 ps
CPU time 1.25 seconds
Started May 07 01:24:11 PM PDT 24
Finished May 07 01:24:15 PM PDT 24
Peak memory 216108 kb
Host smart-b91dbd03-761f-4236-a789-8f47adbdba2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495035770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2495035770
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1946004541
Short name T442
Test name
Test status
Simulation time 39259375 ps
CPU time 0.83 seconds
Started May 07 01:24:07 PM PDT 24
Finished May 07 01:24:10 PM PDT 24
Peak memory 206420 kb
Host smart-f1827a01-f1f2-4f75-8223-55246e1b2c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946004541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1946004541
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2821512984
Short name T328
Test name
Test status
Simulation time 252181333 ps
CPU time 2.75 seconds
Started May 07 01:24:21 PM PDT 24
Finished May 07 01:24:25 PM PDT 24
Peak memory 222612 kb
Host smart-85e61182-fb70-41a7-bb8a-9b59befb3e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821512984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2821512984
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.2141229368
Short name T619
Test name
Test status
Simulation time 15170032 ps
CPU time 0.74 seconds
Started May 07 01:24:05 PM PDT 24
Finished May 07 01:24:08 PM PDT 24
Peak memory 204940 kb
Host smart-d7bbf356-a6b2-4e6d-8ca6-1d9ff61613a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141229368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
2141229368
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.8062777
Short name T338
Test name
Test status
Simulation time 1121727737 ps
CPU time 10.81 seconds
Started May 07 01:24:24 PM PDT 24
Finished May 07 01:24:41 PM PDT 24
Peak memory 232492 kb
Host smart-801ff5ba-73b0-44b4-ab71-78ad7d55b127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8062777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.8062777
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1133019832
Short name T622
Test name
Test status
Simulation time 21916760 ps
CPU time 0.73 seconds
Started May 07 01:24:20 PM PDT 24
Finished May 07 01:24:22 PM PDT 24
Peak memory 205112 kb
Host smart-d3ab231c-f951-4cb6-9a4b-cebc574a5d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133019832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1133019832
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3468066649
Short name T49
Test name
Test status
Simulation time 1110139556 ps
CPU time 6.56 seconds
Started May 07 01:24:11 PM PDT 24
Finished May 07 01:24:20 PM PDT 24
Peak memory 223716 kb
Host smart-f235456c-3694-40e3-8777-e724ef1b949b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468066649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3468066649
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.2414344401
Short name T485
Test name
Test status
Simulation time 1070480707 ps
CPU time 5.21 seconds
Started May 07 01:24:20 PM PDT 24
Finished May 07 01:24:27 PM PDT 24
Peak memory 218896 kb
Host smart-ea209ef5-33ca-4218-a2b8-d2d559a56a53
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2414344401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.2414344401
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1943608760
Short name T415
Test name
Test status
Simulation time 872045194 ps
CPU time 5.87 seconds
Started May 07 01:24:14 PM PDT 24
Finished May 07 01:24:23 PM PDT 24
Peak memory 216184 kb
Host smart-64e897fc-64d4-436c-a07c-16f9b484f607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943608760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1943608760
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2902420293
Short name T580
Test name
Test status
Simulation time 17370600988 ps
CPU time 7.93 seconds
Started May 07 01:24:11 PM PDT 24
Finished May 07 01:24:22 PM PDT 24
Peak memory 216064 kb
Host smart-da357ef6-7d27-42a8-9348-cf9575396448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902420293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2902420293
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.964702692
Short name T398
Test name
Test status
Simulation time 287387671 ps
CPU time 1.26 seconds
Started May 07 01:24:15 PM PDT 24
Finished May 07 01:24:19 PM PDT 24
Peak memory 207760 kb
Host smart-a5a816a6-33c6-425a-922d-07d8e83d5a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964702692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.964702692
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3278037424
Short name T737
Test name
Test status
Simulation time 108847232 ps
CPU time 0.89 seconds
Started May 07 01:24:18 PM PDT 24
Finished May 07 01:24:20 PM PDT 24
Peak memory 206448 kb
Host smart-a6645e6a-ecdf-4971-810d-d5435faef25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278037424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3278037424
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.2136083997
Short name T271
Test name
Test status
Simulation time 3239418504 ps
CPU time 13.56 seconds
Started May 07 01:24:08 PM PDT 24
Finished May 07 01:24:24 PM PDT 24
Peak memory 223784 kb
Host smart-7c451834-50d0-42d4-84ef-83fcf5364fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136083997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2136083997
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1922343654
Short name T424
Test name
Test status
Simulation time 22842121 ps
CPU time 0.68 seconds
Started May 07 01:24:15 PM PDT 24
Finished May 07 01:24:18 PM PDT 24
Peak memory 204348 kb
Host smart-fad9bea1-4054-422a-be49-8b751667d9af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922343654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1922343654
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1972430229
Short name T631
Test name
Test status
Simulation time 51019470 ps
CPU time 0.75 seconds
Started May 07 01:24:18 PM PDT 24
Finished May 07 01:24:20 PM PDT 24
Peak memory 205064 kb
Host smart-f249bb76-4410-4b5e-908c-d376d0e98fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972430229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1972430229
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1135391596
Short name T249
Test name
Test status
Simulation time 817289196 ps
CPU time 10.55 seconds
Started May 07 01:24:21 PM PDT 24
Finished May 07 01:24:34 PM PDT 24
Peak memory 223068 kb
Host smart-b7c32594-4d8e-4cfa-bca7-086e81085c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135391596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1135391596
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2559478324
Short name T284
Test name
Test status
Simulation time 23006068037 ps
CPU time 64.87 seconds
Started May 07 01:24:12 PM PDT 24
Finished May 07 01:25:20 PM PDT 24
Peak memory 219868 kb
Host smart-62bf97eb-1903-4cfe-80a5-7f1476d5331f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559478324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2559478324
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2631995158
Short name T246
Test name
Test status
Simulation time 2298850792 ps
CPU time 8.28 seconds
Started May 07 01:24:25 PM PDT 24
Finished May 07 01:24:36 PM PDT 24
Peak memory 232568 kb
Host smart-f8e31ac5-afa2-4bb9-a79a-12de1d06a0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631995158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2631995158
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.311637116
Short name T157
Test name
Test status
Simulation time 147832794 ps
CPU time 4.52 seconds
Started May 07 01:24:12 PM PDT 24
Finished May 07 01:24:19 PM PDT 24
Peak memory 220228 kb
Host smart-8f1e0430-d166-4fa5-a78d-b14bf478ff07
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=311637116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.311637116
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2655175017
Short name T42
Test name
Test status
Simulation time 73821988 ps
CPU time 1.23 seconds
Started May 07 01:24:21 PM PDT 24
Finished May 07 01:24:24 PM PDT 24
Peak memory 207016 kb
Host smart-f01cffd6-0e3e-4cf1-b681-d63ce27e76bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655175017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2655175017
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2625761971
Short name T80
Test name
Test status
Simulation time 3983383291 ps
CPU time 32.32 seconds
Started May 07 01:24:04 PM PDT 24
Finished May 07 01:24:39 PM PDT 24
Peak memory 216164 kb
Host smart-9d791413-b451-41a1-aa9c-66cc488533f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625761971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2625761971
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1236358380
Short name T552
Test name
Test status
Simulation time 1829368000 ps
CPU time 3.67 seconds
Started May 07 01:24:19 PM PDT 24
Finished May 07 01:24:24 PM PDT 24
Peak memory 216040 kb
Host smart-70123982-c1cf-4d94-b38d-162e3373f1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236358380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1236358380
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.137339108
Short name T416
Test name
Test status
Simulation time 57434157 ps
CPU time 1.37 seconds
Started May 07 01:24:24 PM PDT 24
Finished May 07 01:24:32 PM PDT 24
Peak memory 215908 kb
Host smart-b6a83b6f-705c-447a-9324-be198136d732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137339108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.137339108
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.190908959
Short name T712
Test name
Test status
Simulation time 202901512 ps
CPU time 0.92 seconds
Started May 07 01:24:00 PM PDT 24
Finished May 07 01:24:03 PM PDT 24
Peak memory 206460 kb
Host smart-eb19f0d7-88ea-40b5-b454-63163e1d5b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190908959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.190908959
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2885229715
Short name T339
Test name
Test status
Simulation time 8753799234 ps
CPU time 15.17 seconds
Started May 07 01:24:11 PM PDT 24
Finished May 07 01:24:29 PM PDT 24
Peak memory 223560 kb
Host smart-8cd128d3-5ef7-407a-b8db-6d5af393534d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885229715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2885229715
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1941366967
Short name T649
Test name
Test status
Simulation time 39667631 ps
CPU time 0.71 seconds
Started May 07 01:24:12 PM PDT 24
Finished May 07 01:24:16 PM PDT 24
Peak memory 204940 kb
Host smart-9f287f1e-7c3a-471f-8b10-e3f0cf02ee34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941366967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1941366967
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.398992578
Short name T679
Test name
Test status
Simulation time 16396724 ps
CPU time 0.76 seconds
Started May 07 01:24:12 PM PDT 24
Finished May 07 01:24:15 PM PDT 24
Peak memory 205416 kb
Host smart-93830b17-1923-46c7-8dd5-f27bac46f0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398992578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.398992578
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.4079529966
Short name T713
Test name
Test status
Simulation time 17616685929 ps
CPU time 53.03 seconds
Started May 07 01:24:10 PM PDT 24
Finished May 07 01:25:06 PM PDT 24
Peak memory 232556 kb
Host smart-3d523c36-0784-46c3-9884-e5e77ad7f647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079529966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.4079529966
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2848423501
Short name T273
Test name
Test status
Simulation time 1602727670 ps
CPU time 17.96 seconds
Started May 07 01:24:18 PM PDT 24
Finished May 07 01:24:38 PM PDT 24
Peak memory 218472 kb
Host smart-937028ad-bc3b-46db-99df-8de1ddcd541a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848423501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2848423501
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2560421414
Short name T331
Test name
Test status
Simulation time 379181445 ps
CPU time 5.06 seconds
Started May 07 01:24:11 PM PDT 24
Finished May 07 01:24:19 PM PDT 24
Peak memory 220892 kb
Host smart-108f6a4f-7a7a-4ec3-aff1-86a9604b600f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560421414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2560421414
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1852363504
Short name T494
Test name
Test status
Simulation time 80514229 ps
CPU time 3.69 seconds
Started May 07 01:24:25 PM PDT 24
Finished May 07 01:24:30 PM PDT 24
Peak memory 222656 kb
Host smart-9be96b95-4725-4be9-86e7-504a19c901f5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1852363504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1852363504
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1601075177
Short name T420
Test name
Test status
Simulation time 8055040960 ps
CPU time 10.06 seconds
Started May 07 01:24:16 PM PDT 24
Finished May 07 01:24:28 PM PDT 24
Peak memory 216192 kb
Host smart-7aa24ea1-5ba7-45ab-a1cf-19e819752abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601075177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1601075177
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3941595695
Short name T435
Test name
Test status
Simulation time 2801073418 ps
CPU time 3.18 seconds
Started May 07 01:24:18 PM PDT 24
Finished May 07 01:24:23 PM PDT 24
Peak memory 216072 kb
Host smart-ff3e5e59-e362-4dac-936d-f169f2330ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941595695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3941595695
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3066863580
Short name T586
Test name
Test status
Simulation time 711631978 ps
CPU time 5.95 seconds
Started May 07 01:24:06 PM PDT 24
Finished May 07 01:24:14 PM PDT 24
Peak memory 216072 kb
Host smart-bd6cdacd-dcf4-4b11-bc6e-1afedb50859d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066863580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3066863580
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3083378334
Short name T505
Test name
Test status
Simulation time 18224994 ps
CPU time 0.73 seconds
Started May 07 01:24:11 PM PDT 24
Finished May 07 01:24:15 PM PDT 24
Peak memory 205396 kb
Host smart-7bbb8d9e-35fc-4d57-9a69-3a1fd5b328a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083378334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3083378334
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2447814308
Short name T176
Test name
Test status
Simulation time 354728003 ps
CPU time 5.05 seconds
Started May 07 01:24:16 PM PDT 24
Finished May 07 01:24:23 PM PDT 24
Peak memory 223840 kb
Host smart-a330765f-e63e-4189-a38d-1876d03d6736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447814308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2447814308
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.164020238
Short name T437
Test name
Test status
Simulation time 245288984 ps
CPU time 0.74 seconds
Started May 07 01:24:23 PM PDT 24
Finished May 07 01:24:26 PM PDT 24
Peak memory 204320 kb
Host smart-3ecc743d-67a4-46f6-9749-4e44597dad25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164020238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.164020238
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.934571449
Short name T168
Test name
Test status
Simulation time 240514694 ps
CPU time 5.11 seconds
Started May 07 01:24:13 PM PDT 24
Finished May 07 01:24:21 PM PDT 24
Peak memory 234244 kb
Host smart-62685c7a-d101-4232-81ef-3489f19fe392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934571449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.934571449
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3357104563
Short name T444
Test name
Test status
Simulation time 126712109 ps
CPU time 0.79 seconds
Started May 07 01:24:11 PM PDT 24
Finished May 07 01:24:14 PM PDT 24
Peak memory 206460 kb
Host smart-f1c0f4a5-a5f9-482e-a008-b832d93531da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357104563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3357104563
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_intercept.4096919649
Short name T254
Test name
Test status
Simulation time 71536836 ps
CPU time 2.65 seconds
Started May 07 01:24:15 PM PDT 24
Finished May 07 01:24:20 PM PDT 24
Peak memory 222248 kb
Host smart-d448d80a-69aa-413d-af34-016a4c6304c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096919649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.4096919649
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2414716231
Short name T113
Test name
Test status
Simulation time 859734462 ps
CPU time 15.61 seconds
Started May 07 01:24:14 PM PDT 24
Finished May 07 01:24:33 PM PDT 24
Peak memory 227344 kb
Host smart-64411d8c-d74f-4f9d-90a9-3a5f029aab47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414716231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2414716231
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.4123162773
Short name T179
Test name
Test status
Simulation time 36514440763 ps
CPU time 21.44 seconds
Started May 07 01:24:08 PM PDT 24
Finished May 07 01:24:31 PM PDT 24
Peak memory 232504 kb
Host smart-ab396792-944c-424d-8db3-ef91cb3180a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123162773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.4123162773
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2892943895
Short name T78
Test name
Test status
Simulation time 536898794 ps
CPU time 5.52 seconds
Started May 07 01:24:27 PM PDT 24
Finished May 07 01:24:34 PM PDT 24
Peak memory 222692 kb
Host smart-982dd4d6-0b40-4595-9bd5-291c94e33a2f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2892943895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2892943895
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.321603464
Short name T34
Test name
Test status
Simulation time 119300385 ps
CPU time 1.03 seconds
Started May 07 01:24:12 PM PDT 24
Finished May 07 01:24:16 PM PDT 24
Peak memory 206308 kb
Host smart-b03876d8-ae2e-48df-9d70-77b17b3d3e8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321603464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.321603464
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2789699743
Short name T640
Test name
Test status
Simulation time 9002807516 ps
CPU time 11.63 seconds
Started May 07 01:24:16 PM PDT 24
Finished May 07 01:24:29 PM PDT 24
Peak memory 216112 kb
Host smart-59ae5132-cf94-481c-adee-305a3e57f46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789699743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2789699743
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2857331589
Short name T723
Test name
Test status
Simulation time 180197258 ps
CPU time 2.73 seconds
Started May 07 01:24:24 PM PDT 24
Finished May 07 01:24:29 PM PDT 24
Peak memory 216024 kb
Host smart-6507f34f-9912-48c4-9be6-14617e319ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857331589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2857331589
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.40636680
Short name T724
Test name
Test status
Simulation time 159992860 ps
CPU time 0.86 seconds
Started May 07 01:24:23 PM PDT 24
Finished May 07 01:24:26 PM PDT 24
Peak memory 206372 kb
Host smart-32ceb662-27a8-4a89-a584-a0f148c10d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40636680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.40636680
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.1983695891
Short name T321
Test name
Test status
Simulation time 20246770367 ps
CPU time 32.06 seconds
Started May 07 01:24:08 PM PDT 24
Finished May 07 01:24:43 PM PDT 24
Peak memory 232952 kb
Host smart-7ea9ada8-18a3-478e-80d2-759cc8851fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983695891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1983695891
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1363320957
Short name T514
Test name
Test status
Simulation time 27760160 ps
CPU time 0.73 seconds
Started May 07 01:24:11 PM PDT 24
Finished May 07 01:24:15 PM PDT 24
Peak memory 204972 kb
Host smart-c9a7769e-8016-486a-b4a3-ffd3f5c2fc77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363320957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1363320957
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1277279170
Short name T446
Test name
Test status
Simulation time 18612319 ps
CPU time 0.8 seconds
Started May 07 01:24:23 PM PDT 24
Finished May 07 01:24:25 PM PDT 24
Peak memory 206144 kb
Host smart-fd461b38-2e02-4db6-9aad-9094b69a2fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277279170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1277279170
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3907758521
Short name T303
Test name
Test status
Simulation time 2919277362 ps
CPU time 28.2 seconds
Started May 07 01:24:23 PM PDT 24
Finished May 07 01:24:53 PM PDT 24
Peak memory 232584 kb
Host smart-d449d347-c35e-4002-9641-f14fbb1c6d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907758521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3907758521
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2495807131
Short name T377
Test name
Test status
Simulation time 75988927029 ps
CPU time 90.75 seconds
Started May 07 01:24:15 PM PDT 24
Finished May 07 01:25:49 PM PDT 24
Peak memory 232488 kb
Host smart-57e4311a-c958-460a-a071-e8bb63991a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495807131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2495807131
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3917902536
Short name T231
Test name
Test status
Simulation time 16755823063 ps
CPU time 42.61 seconds
Started May 07 01:24:23 PM PDT 24
Finished May 07 01:25:07 PM PDT 24
Peak memory 228100 kb
Host smart-25bae175-1b54-4807-9677-0bae004c50b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917902536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3917902536
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.4271064342
Short name T703
Test name
Test status
Simulation time 1047247302 ps
CPU time 10.05 seconds
Started May 07 01:24:12 PM PDT 24
Finished May 07 01:24:24 PM PDT 24
Peak memory 221980 kb
Host smart-1ee42ff8-a725-4199-86ab-47ad8b305943
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4271064342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.4271064342
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1437106805
Short name T413
Test name
Test status
Simulation time 6520799247 ps
CPU time 45.51 seconds
Started May 07 01:24:19 PM PDT 24
Finished May 07 01:25:06 PM PDT 24
Peak memory 216232 kb
Host smart-b4a6a2b7-8817-40ec-9796-d11df85a5a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437106805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1437106805
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3194688804
Short name T447
Test name
Test status
Simulation time 42738339303 ps
CPU time 20.51 seconds
Started May 07 01:24:24 PM PDT 24
Finished May 07 01:24:47 PM PDT 24
Peak memory 216068 kb
Host smart-ec668539-df37-471d-898e-fc4dc03ecfcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194688804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3194688804
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.602911545
Short name T55
Test name
Test status
Simulation time 36237571 ps
CPU time 0.84 seconds
Started May 07 01:24:26 PM PDT 24
Finished May 07 01:24:29 PM PDT 24
Peak memory 207444 kb
Host smart-43731218-4347-4905-8bc2-37fbc6814275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602911545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.602911545
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.989848700
Short name T583
Test name
Test status
Simulation time 93488156 ps
CPU time 1.01 seconds
Started May 07 01:24:15 PM PDT 24
Finished May 07 01:24:19 PM PDT 24
Peak memory 206380 kb
Host smart-92d387b1-bc50-42e3-9978-dd2a6120a2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989848700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.989848700
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.316442739
Short name T30
Test name
Test status
Simulation time 27723313149 ps
CPU time 37.16 seconds
Started May 07 01:24:21 PM PDT 24
Finished May 07 01:25:00 PM PDT 24
Peak memory 232204 kb
Host smart-167e9b6e-edb5-4d0e-9329-9e9d58a16470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316442739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.316442739
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3291897034
Short name T736
Test name
Test status
Simulation time 35569044 ps
CPU time 0.74 seconds
Started May 07 01:23:33 PM PDT 24
Finished May 07 01:23:36 PM PDT 24
Peak memory 204976 kb
Host smart-4adc6f12-87bb-437c-850b-84ac7ca1ae5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291897034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
291897034
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.688327332
Short name T237
Test name
Test status
Simulation time 664857158 ps
CPU time 7.2 seconds
Started May 07 01:23:24 PM PDT 24
Finished May 07 01:23:32 PM PDT 24
Peak memory 218928 kb
Host smart-86de87e0-07e5-4fcb-bf7d-99106a7533b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688327332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.688327332
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2718616265
Short name T445
Test name
Test status
Simulation time 103819555 ps
CPU time 0.72 seconds
Started May 07 01:23:10 PM PDT 24
Finished May 07 01:23:11 PM PDT 24
Peak memory 205052 kb
Host smart-316aafe6-fc04-404d-afd2-5875e20a328d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718616265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2718616265
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_intercept.4018863397
Short name T50
Test name
Test status
Simulation time 10374135749 ps
CPU time 10.51 seconds
Started May 07 01:23:15 PM PDT 24
Finished May 07 01:23:26 PM PDT 24
Peak memory 224024 kb
Host smart-9ea2cfe0-d190-4a42-9a02-afd4776bb577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018863397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.4018863397
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.4110089868
Short name T694
Test name
Test status
Simulation time 49492962 ps
CPU time 1.05 seconds
Started May 07 01:23:18 PM PDT 24
Finished May 07 01:23:21 PM PDT 24
Peak memory 216472 kb
Host smart-a261183a-a8e0-4eed-b8b6-44b0b01f62ae
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110089868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.4110089868
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1185217578
Short name T213
Test name
Test status
Simulation time 839598164 ps
CPU time 4.38 seconds
Started May 07 01:23:12 PM PDT 24
Finished May 07 01:23:17 PM PDT 24
Peak memory 222136 kb
Host smart-59997564-3f55-46be-8b95-831672d2048a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185217578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1185217578
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3803311671
Short name T324
Test name
Test status
Simulation time 3238068920 ps
CPU time 9.25 seconds
Started May 07 01:23:41 PM PDT 24
Finished May 07 01:23:52 PM PDT 24
Peak memory 223124 kb
Host smart-2d414d19-8b28-41ac-bffb-f41fcc1a39c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803311671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3803311671
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.4064128914
Short name T648
Test name
Test status
Simulation time 304301068 ps
CPU time 4.09 seconds
Started May 07 01:23:17 PM PDT 24
Finished May 07 01:23:23 PM PDT 24
Peak memory 219696 kb
Host smart-117dbf10-3b4e-4f1b-a26d-667ec56e0c13
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4064128914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.4064128914
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1303044492
Short name T661
Test name
Test status
Simulation time 3870068166 ps
CPU time 6.54 seconds
Started May 07 01:23:14 PM PDT 24
Finished May 07 01:23:22 PM PDT 24
Peak memory 216120 kb
Host smart-3772f5f2-d31a-4080-a067-d67b20130966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303044492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1303044492
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3497257329
Short name T564
Test name
Test status
Simulation time 243057041 ps
CPU time 2.98 seconds
Started May 07 01:23:21 PM PDT 24
Finished May 07 01:23:25 PM PDT 24
Peak memory 216480 kb
Host smart-d593af40-7b8a-4851-b4f6-d1c90c6b6041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497257329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3497257329
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1098438154
Short name T438
Test name
Test status
Simulation time 78341782 ps
CPU time 0.96 seconds
Started May 07 01:23:19 PM PDT 24
Finished May 07 01:23:21 PM PDT 24
Peak memory 206444 kb
Host smart-6a851430-8c6e-4fcb-ad6d-d14544191148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098438154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1098438154
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3148618664
Short name T32
Test name
Test status
Simulation time 12779210 ps
CPU time 0.72 seconds
Started May 07 01:24:25 PM PDT 24
Finished May 07 01:24:28 PM PDT 24
Peak memory 204956 kb
Host smart-8550f9a8-a962-4f3e-86d3-81c128641f79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148618664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3148618664
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1223964612
Short name T609
Test name
Test status
Simulation time 44937823 ps
CPU time 0.72 seconds
Started May 07 01:24:16 PM PDT 24
Finished May 07 01:24:19 PM PDT 24
Peak memory 206472 kb
Host smart-2f62afe8-5342-4054-9ed5-9703be8fffe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223964612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1223964612
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.4227058849
Short name T362
Test name
Test status
Simulation time 5245892881 ps
CPU time 71.94 seconds
Started May 07 01:24:27 PM PDT 24
Finished May 07 01:25:40 PM PDT 24
Peak memory 240772 kb
Host smart-5a2c753f-110a-4ae8-9a59-7de69df307b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227058849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.4227058849
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.667401525
Short name T177
Test name
Test status
Simulation time 471663539 ps
CPU time 6.34 seconds
Started May 07 01:24:14 PM PDT 24
Finished May 07 01:24:24 PM PDT 24
Peak memory 232164 kb
Host smart-e5cb662c-56cd-4fdc-9021-d02025fde503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667401525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.667401525
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2793360951
Short name T315
Test name
Test status
Simulation time 7959681041 ps
CPU time 28.06 seconds
Started May 07 01:24:24 PM PDT 24
Finished May 07 01:24:54 PM PDT 24
Peak memory 224320 kb
Host smart-1f232026-e121-4c23-8970-ecaf71b9eed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793360951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2793360951
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2015656158
Short name T223
Test name
Test status
Simulation time 10073434589 ps
CPU time 10.94 seconds
Started May 07 01:24:26 PM PDT 24
Finished May 07 01:24:38 PM PDT 24
Peak memory 217944 kb
Host smart-dc2bf636-cde9-4ebb-a636-ad01a8b4cb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015656158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2015656158
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1028549545
Short name T483
Test name
Test status
Simulation time 683464507 ps
CPU time 4.19 seconds
Started May 07 01:24:33 PM PDT 24
Finished May 07 01:24:39 PM PDT 24
Peak memory 218912 kb
Host smart-90303b95-664d-4f44-a1d3-55d0604d07cb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1028549545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1028549545
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2117374209
Short name T626
Test name
Test status
Simulation time 22448743844 ps
CPU time 56.5 seconds
Started May 07 01:24:26 PM PDT 24
Finished May 07 01:25:24 PM PDT 24
Peak memory 216208 kb
Host smart-8e951bdd-c126-4caf-be72-551d3fb87af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117374209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2117374209
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2013665110
Short name T525
Test name
Test status
Simulation time 3163268760 ps
CPU time 5.6 seconds
Started May 07 01:24:24 PM PDT 24
Finished May 07 01:24:32 PM PDT 24
Peak memory 216008 kb
Host smart-2abb201d-3ea3-43e0-8fd6-b687d01846c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013665110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2013665110
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3851652056
Short name T495
Test name
Test status
Simulation time 701674208 ps
CPU time 4.91 seconds
Started May 07 01:24:22 PM PDT 24
Finished May 07 01:24:29 PM PDT 24
Peak memory 215936 kb
Host smart-dbcdb4e6-b8cd-4f69-88ca-8c74439345da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851652056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3851652056
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.4027603059
Short name T509
Test name
Test status
Simulation time 17720514 ps
CPU time 0.75 seconds
Started May 07 01:24:12 PM PDT 24
Finished May 07 01:24:16 PM PDT 24
Peak memory 205592 kb
Host smart-968187ca-d419-4710-b30e-93f65cc35b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027603059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.4027603059
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.4249128538
Short name T503
Test name
Test status
Simulation time 34714957 ps
CPU time 0.72 seconds
Started May 07 01:24:22 PM PDT 24
Finished May 07 01:24:25 PM PDT 24
Peak memory 205012 kb
Host smart-69005b32-ab75-4a7b-bb6a-94fb9440df25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249128538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
4249128538
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3301763604
Short name T682
Test name
Test status
Simulation time 63535204 ps
CPU time 0.74 seconds
Started May 07 01:24:42 PM PDT 24
Finished May 07 01:24:44 PM PDT 24
Peak memory 206104 kb
Host smart-614b35e8-3373-410e-9805-d3dc936bf9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301763604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3301763604
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.129040656
Short name T526
Test name
Test status
Simulation time 1609086017 ps
CPU time 10.62 seconds
Started May 07 01:24:29 PM PDT 24
Finished May 07 01:24:41 PM PDT 24
Peak memory 219776 kb
Host smart-e98c1b02-cebc-4450-b2d9-edc48b67eb26
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=129040656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dire
ct.129040656
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1617320133
Short name T406
Test name
Test status
Simulation time 1594388997 ps
CPU time 4.58 seconds
Started May 07 01:24:27 PM PDT 24
Finished May 07 01:24:33 PM PDT 24
Peak memory 216108 kb
Host smart-a48a4340-5978-40fb-9e42-f6149b129d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617320133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1617320133
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.971144120
Short name T511
Test name
Test status
Simulation time 6914668537 ps
CPU time 22.29 seconds
Started May 07 01:24:32 PM PDT 24
Finished May 07 01:24:56 PM PDT 24
Peak memory 216140 kb
Host smart-afad6bd2-2cc5-4648-b741-b2a4cdb3da62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971144120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.971144120
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3277916581
Short name T606
Test name
Test status
Simulation time 959647831 ps
CPU time 8.96 seconds
Started May 07 01:24:23 PM PDT 24
Finished May 07 01:24:34 PM PDT 24
Peak memory 216056 kb
Host smart-83ed7d22-f43a-4113-b9e5-e1602853f83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277916581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3277916581
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.602240645
Short name T81
Test name
Test status
Simulation time 234112723 ps
CPU time 1.3 seconds
Started May 07 01:24:22 PM PDT 24
Finished May 07 01:24:25 PM PDT 24
Peak memory 206376 kb
Host smart-60af30c6-4633-4fec-a355-b0b430d34d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602240645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.602240645
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.4210627528
Short name T187
Test name
Test status
Simulation time 521340933 ps
CPU time 7.15 seconds
Started May 07 01:24:20 PM PDT 24
Finished May 07 01:24:29 PM PDT 24
Peak memory 234080 kb
Host smart-9f2972be-b29d-4d0a-9deb-67982425e0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210627528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.4210627528
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1336289914
Short name T650
Test name
Test status
Simulation time 12932987 ps
CPU time 0.69 seconds
Started May 07 01:24:32 PM PDT 24
Finished May 07 01:24:34 PM PDT 24
Peak memory 204904 kb
Host smart-54a83ed3-d294-4a02-ae50-b1f7ca739de8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336289914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1336289914
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.20546706
Short name T588
Test name
Test status
Simulation time 66774613 ps
CPU time 0.73 seconds
Started May 07 01:24:37 PM PDT 24
Finished May 07 01:24:39 PM PDT 24
Peak memory 205088 kb
Host smart-28aedb72-2f08-414f-a3f6-dccd98db5bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20546706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.20546706
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1382724038
Short name T372
Test name
Test status
Simulation time 14647191767 ps
CPU time 60.21 seconds
Started May 07 01:24:29 PM PDT 24
Finished May 07 01:25:30 PM PDT 24
Peak memory 239360 kb
Host smart-df98b158-520a-4cf8-8d90-140256070ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382724038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1382724038
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2624763906
Short name T592
Test name
Test status
Simulation time 560024155 ps
CPU time 4.29 seconds
Started May 07 01:24:38 PM PDT 24
Finished May 07 01:24:43 PM PDT 24
Peak memory 219160 kb
Host smart-68622937-5e55-4f49-abd7-d7985ada6c07
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2624763906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2624763906
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3255832844
Short name T600
Test name
Test status
Simulation time 2051244647 ps
CPU time 11.52 seconds
Started May 07 01:24:28 PM PDT 24
Finished May 07 01:24:41 PM PDT 24
Peak memory 216256 kb
Host smart-cc2d1e17-1abd-46bc-ab9c-cb87798d2633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255832844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3255832844
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.336980443
Short name T475
Test name
Test status
Simulation time 17462707575 ps
CPU time 9.81 seconds
Started May 07 01:24:27 PM PDT 24
Finished May 07 01:24:39 PM PDT 24
Peak memory 216004 kb
Host smart-c6d6278f-9d93-4010-bb42-fd369334f39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336980443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.336980443
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.986679023
Short name T559
Test name
Test status
Simulation time 147177290 ps
CPU time 2.03 seconds
Started May 07 01:24:29 PM PDT 24
Finished May 07 01:24:33 PM PDT 24
Peak memory 216112 kb
Host smart-edb56531-4a5a-49dd-ade2-db291558c26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986679023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.986679023
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1453972980
Short name T474
Test name
Test status
Simulation time 338025356 ps
CPU time 1.05 seconds
Started May 07 01:24:30 PM PDT 24
Finished May 07 01:24:32 PM PDT 24
Peak memory 206492 kb
Host smart-e943016f-7729-4866-96b4-56ccb405ae29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453972980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1453972980
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.2163594925
Short name T232
Test name
Test status
Simulation time 8104640269 ps
CPU time 16.39 seconds
Started May 07 01:24:26 PM PDT 24
Finished May 07 01:24:44 PM PDT 24
Peak memory 223508 kb
Host smart-ab749f4f-0837-4c39-a5d4-44bb76a39d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163594925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2163594925
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2392907045
Short name T31
Test name
Test status
Simulation time 11198752 ps
CPU time 0.7 seconds
Started May 07 01:24:36 PM PDT 24
Finished May 07 01:24:37 PM PDT 24
Peak memory 204376 kb
Host smart-98583c9c-0c63-408f-ab7c-6927caa21094
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392907045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2392907045
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3996987553
Short name T610
Test name
Test status
Simulation time 208215403 ps
CPU time 0.78 seconds
Started May 07 01:24:30 PM PDT 24
Finished May 07 01:24:32 PM PDT 24
Peak memory 205072 kb
Host smart-ced88736-fc7c-47a1-b2dc-6ce884cf31dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996987553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3996987553
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3274508024
Short name T297
Test name
Test status
Simulation time 3670714727 ps
CPU time 52.2 seconds
Started May 07 01:24:29 PM PDT 24
Finished May 07 01:25:22 PM PDT 24
Peak memory 248972 kb
Host smart-ac1caf71-bd90-46e6-960c-2f0fdcbec936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274508024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3274508024
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2720579649
Short name T240
Test name
Test status
Simulation time 7346751110 ps
CPU time 62.81 seconds
Started May 07 01:24:34 PM PDT 24
Finished May 07 01:25:38 PM PDT 24
Peak memory 229236 kb
Host smart-7e54a862-0700-4995-bd3e-ab6851ab124c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720579649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2720579649
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2611341215
Short name T204
Test name
Test status
Simulation time 82346651932 ps
CPU time 32 seconds
Started May 07 01:24:23 PM PDT 24
Finished May 07 01:24:57 PM PDT 24
Peak memory 231140 kb
Host smart-b7a66737-c9ef-4763-87c1-ad5dcaf5ee7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611341215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2611341215
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1530711387
Short name T221
Test name
Test status
Simulation time 3662814176 ps
CPU time 6.13 seconds
Started May 07 01:24:28 PM PDT 24
Finished May 07 01:24:35 PM PDT 24
Peak memory 224280 kb
Host smart-9343f6ef-3fea-41f5-a0cc-1f16f97fc837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530711387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1530711387
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1557270821
Short name T543
Test name
Test status
Simulation time 3721172564 ps
CPU time 11.32 seconds
Started May 07 01:24:43 PM PDT 24
Finished May 07 01:24:56 PM PDT 24
Peak memory 222484 kb
Host smart-6d9b1f97-7736-4523-b062-618cf80e755a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1557270821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1557270821
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3745611377
Short name T103
Test name
Test status
Simulation time 79979270530 ps
CPU time 20.2 seconds
Started May 07 01:24:36 PM PDT 24
Finished May 07 01:24:57 PM PDT 24
Peak memory 216004 kb
Host smart-95018c61-8d1b-4f2a-a545-29a4994f49c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745611377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3745611377
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1216474041
Short name T419
Test name
Test status
Simulation time 188132854 ps
CPU time 1.31 seconds
Started May 07 01:24:46 PM PDT 24
Finished May 07 01:24:49 PM PDT 24
Peak memory 216172 kb
Host smart-615c3550-4d71-4e7c-a319-78321948bf8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216474041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1216474041
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2092830
Short name T519
Test name
Test status
Simulation time 85299684 ps
CPU time 0.8 seconds
Started May 07 01:24:29 PM PDT 24
Finished May 07 01:24:31 PM PDT 24
Peak memory 205460 kb
Host smart-bd2721e5-26c0-4824-89eb-2f9174722e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2092830
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.2196817899
Short name T425
Test name
Test status
Simulation time 13197341 ps
CPU time 0.69 seconds
Started May 07 01:24:23 PM PDT 24
Finished May 07 01:24:25 PM PDT 24
Peak memory 204924 kb
Host smart-72524b72-e3c2-4b6f-9143-d34631bc1fed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196817899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
2196817899
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1206741029
Short name T740
Test name
Test status
Simulation time 29208004 ps
CPU time 0.84 seconds
Started May 07 01:24:38 PM PDT 24
Finished May 07 01:24:39 PM PDT 24
Peak memory 206024 kb
Host smart-a0cbd99f-5e15-40b4-a06a-26bdcf152494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206741029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1206741029
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2021438117
Short name T363
Test name
Test status
Simulation time 1676783271 ps
CPU time 21.15 seconds
Started May 07 01:24:35 PM PDT 24
Finished May 07 01:24:57 PM PDT 24
Peak memory 248900 kb
Host smart-720b8191-4f7e-4c9b-9354-a60565d4be7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021438117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2021438117
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2797475508
Short name T192
Test name
Test status
Simulation time 1984045856 ps
CPU time 8.46 seconds
Started May 07 01:24:51 PM PDT 24
Finished May 07 01:25:01 PM PDT 24
Peak memory 223728 kb
Host smart-04b363a8-f440-4bf2-8f4f-dbe37a974a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797475508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2797475508
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1762760710
Short name T356
Test name
Test status
Simulation time 497028052 ps
CPU time 10.48 seconds
Started May 07 01:24:49 PM PDT 24
Finished May 07 01:25:00 PM PDT 24
Peak memory 219616 kb
Host smart-85a6fc04-7b96-45a6-ada2-967bd6fcbbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762760710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1762760710
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.226255963
Short name T281
Test name
Test status
Simulation time 276944761 ps
CPU time 2.86 seconds
Started May 07 01:24:30 PM PDT 24
Finished May 07 01:24:35 PM PDT 24
Peak memory 218440 kb
Host smart-a407aa41-fee4-4d60-9f96-36661404aae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226255963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.226255963
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1944864952
Short name T721
Test name
Test status
Simulation time 866252508 ps
CPU time 4.98 seconds
Started May 07 01:24:25 PM PDT 24
Finished May 07 01:24:32 PM PDT 24
Peak memory 222780 kb
Host smart-bd94e323-c82d-45f2-a71b-450ceedc80fd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1944864952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1944864952
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.972253798
Short name T375
Test name
Test status
Simulation time 108994549 ps
CPU time 1.1 seconds
Started May 07 01:24:25 PM PDT 24
Finished May 07 01:24:28 PM PDT 24
Peak memory 206700 kb
Host smart-d0ecbcb4-c2af-484e-a30a-bc04a415cf25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972253798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stres
s_all.972253798
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1366252006
Short name T385
Test name
Test status
Simulation time 11126746922 ps
CPU time 52.8 seconds
Started May 07 01:24:36 PM PDT 24
Finished May 07 01:25:30 PM PDT 24
Peak memory 216060 kb
Host smart-1fa8104e-60f7-4d12-9287-ef47eaac70a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366252006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1366252006
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3524317060
Short name T574
Test name
Test status
Simulation time 2427830433 ps
CPU time 3.24 seconds
Started May 07 01:24:32 PM PDT 24
Finished May 07 01:24:36 PM PDT 24
Peak memory 216076 kb
Host smart-78f25dc8-7295-4ce0-9da5-050402539356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524317060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3524317060
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.184689460
Short name T730
Test name
Test status
Simulation time 1504358442 ps
CPU time 2.35 seconds
Started May 07 01:24:27 PM PDT 24
Finished May 07 01:24:31 PM PDT 24
Peak memory 216076 kb
Host smart-cdda52c1-f875-43f3-a3ae-1097db34ee17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184689460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.184689460
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.792482537
Short name T449
Test name
Test status
Simulation time 89204182 ps
CPU time 0.91 seconds
Started May 07 01:24:34 PM PDT 24
Finished May 07 01:24:36 PM PDT 24
Peak memory 206460 kb
Host smart-f99fbfae-1661-44c7-8eb5-cef2ae9f5dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792482537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.792482537
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1177280142
Short name T502
Test name
Test status
Simulation time 10830403 ps
CPU time 0.73 seconds
Started May 07 01:24:42 PM PDT 24
Finished May 07 01:24:44 PM PDT 24
Peak memory 204948 kb
Host smart-20fe38d1-c6f3-42cd-aacf-b9382629d0ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177280142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1177280142
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2284801851
Short name T434
Test name
Test status
Simulation time 20935905 ps
CPU time 0.74 seconds
Started May 07 01:24:31 PM PDT 24
Finished May 07 01:24:33 PM PDT 24
Peak memory 205088 kb
Host smart-84216283-759d-4bfe-a479-80c6f0559b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284801851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2284801851
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2742197441
Short name T567
Test name
Test status
Simulation time 16322161764 ps
CPU time 53.81 seconds
Started May 07 01:24:44 PM PDT 24
Finished May 07 01:25:40 PM PDT 24
Peak memory 232564 kb
Host smart-a18a5174-e053-4ae7-995f-9981e706cd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742197441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2742197441
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3912412748
Short name T280
Test name
Test status
Simulation time 1919943803 ps
CPU time 6.39 seconds
Started May 07 01:24:54 PM PDT 24
Finished May 07 01:25:02 PM PDT 24
Peak memory 220840 kb
Host smart-ed253081-d605-4ca4-b80d-81bbc5a8f60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912412748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3912412748
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.518769292
Short name T457
Test name
Test status
Simulation time 3665032443 ps
CPU time 9.9 seconds
Started May 07 01:24:45 PM PDT 24
Finished May 07 01:24:57 PM PDT 24
Peak memory 221220 kb
Host smart-e32c4319-927f-4c10-9499-62f5887738c0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=518769292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.518769292
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.4151477284
Short name T715
Test name
Test status
Simulation time 834066799 ps
CPU time 12.97 seconds
Started May 07 01:24:34 PM PDT 24
Finished May 07 01:24:48 PM PDT 24
Peak memory 216472 kb
Host smart-16796ed6-85fc-4245-8519-4c4d88e73821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151477284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.4151477284
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.717599078
Short name T549
Test name
Test status
Simulation time 9285587541 ps
CPU time 24.66 seconds
Started May 07 01:24:34 PM PDT 24
Finished May 07 01:25:00 PM PDT 24
Peak memory 216012 kb
Host smart-472c40af-a04f-45f1-aece-36987bfbd9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717599078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.717599078
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.4117364117
Short name T414
Test name
Test status
Simulation time 246521482 ps
CPU time 1.31 seconds
Started May 07 01:24:44 PM PDT 24
Finished May 07 01:24:47 PM PDT 24
Peak memory 207908 kb
Host smart-c7393701-6fc8-47f2-8479-1a34abfcca18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117364117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.4117364117
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3965461229
Short name T639
Test name
Test status
Simulation time 102076405 ps
CPU time 0.81 seconds
Started May 07 01:24:44 PM PDT 24
Finished May 07 01:24:46 PM PDT 24
Peak memory 205488 kb
Host smart-070c2093-19fb-4974-b91d-ff0da3cd2004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965461229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3965461229
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2853030645
Short name T618
Test name
Test status
Simulation time 1714801383 ps
CPU time 6.72 seconds
Started May 07 01:24:41 PM PDT 24
Finished May 07 01:24:49 PM PDT 24
Peak memory 218872 kb
Host smart-dd00a13d-d72f-4daf-9ba3-8e79ced5a2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853030645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2853030645
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.4286667111
Short name T638
Test name
Test status
Simulation time 15772584 ps
CPU time 0.78 seconds
Started May 07 01:24:39 PM PDT 24
Finished May 07 01:24:41 PM PDT 24
Peak memory 205084 kb
Host smart-e8fb6d1d-fd77-4c6e-806c-221bdc5c4173
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286667111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
4286667111
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3558180189
Short name T274
Test name
Test status
Simulation time 1934875319 ps
CPU time 5.02 seconds
Started May 07 01:24:44 PM PDT 24
Finished May 07 01:24:51 PM PDT 24
Peak memory 218568 kb
Host smart-6b69fa87-fa99-4e70-98bb-61999c32b344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558180189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3558180189
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3289333330
Short name T480
Test name
Test status
Simulation time 29854120 ps
CPU time 0.74 seconds
Started May 07 01:24:37 PM PDT 24
Finished May 07 01:24:39 PM PDT 24
Peak memory 206436 kb
Host smart-0f84c053-e7c1-41e1-9689-cc033a0725da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289333330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3289333330
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_intercept.876829416
Short name T278
Test name
Test status
Simulation time 259846119 ps
CPU time 5.71 seconds
Started May 07 01:24:43 PM PDT 24
Finished May 07 01:24:50 PM PDT 24
Peak memory 218780 kb
Host smart-155f98a3-e92b-4f82-bcc3-682d7577eaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876829416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.876829416
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2517779660
Short name T108
Test name
Test status
Simulation time 434514393 ps
CPU time 12.79 seconds
Started May 07 01:24:52 PM PDT 24
Finished May 07 01:25:06 PM PDT 24
Peak memory 230840 kb
Host smart-b9c96b35-6f60-4e33-939e-396924698f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517779660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2517779660
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.564554853
Short name T166
Test name
Test status
Simulation time 7576637606 ps
CPU time 13.09 seconds
Started May 07 01:24:42 PM PDT 24
Finished May 07 01:24:56 PM PDT 24
Peak memory 231684 kb
Host smart-d626a7f4-6784-4fa3-8402-27bec825944b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564554853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.564554853
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3912329349
Short name T710
Test name
Test status
Simulation time 1123134486 ps
CPU time 7.45 seconds
Started May 07 01:24:35 PM PDT 24
Finished May 07 01:24:43 PM PDT 24
Peak memory 222760 kb
Host smart-75fa7eed-8064-4cd4-9181-8b9d62ab0ee6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3912329349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3912329349
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2360870361
Short name T397
Test name
Test status
Simulation time 6584010183 ps
CPU time 27.98 seconds
Started May 07 01:24:41 PM PDT 24
Finished May 07 01:25:10 PM PDT 24
Peak memory 216352 kb
Host smart-4f72caf7-32f1-496c-bb43-97bbe924927a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360870361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2360870361
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1356192833
Short name T518
Test name
Test status
Simulation time 217136954 ps
CPU time 2.02 seconds
Started May 07 01:24:49 PM PDT 24
Finished May 07 01:24:52 PM PDT 24
Peak memory 215576 kb
Host smart-e82ddf5b-0352-4958-a350-73366acfdd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356192833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1356192833
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2469135412
Short name T57
Test name
Test status
Simulation time 148063056 ps
CPU time 1.69 seconds
Started May 07 01:24:44 PM PDT 24
Finished May 07 01:24:48 PM PDT 24
Peak memory 216080 kb
Host smart-de64ca94-be97-4d39-a190-399cf2db6e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469135412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2469135412
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2362401604
Short name T531
Test name
Test status
Simulation time 49021135 ps
CPU time 0.83 seconds
Started May 07 01:24:43 PM PDT 24
Finished May 07 01:24:45 PM PDT 24
Peak memory 205432 kb
Host smart-e4846615-65b9-4ee1-b8ab-75b16ce00517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362401604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2362401604
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.3052929385
Short name T239
Test name
Test status
Simulation time 7441322470 ps
CPU time 16.27 seconds
Started May 07 01:24:31 PM PDT 24
Finished May 07 01:24:49 PM PDT 24
Peak memory 232436 kb
Host smart-fbf355a7-37ed-4e2a-afc2-c22f40c5965a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052929385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3052929385
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2397828441
Short name T584
Test name
Test status
Simulation time 18152465 ps
CPU time 0.73 seconds
Started May 07 01:24:44 PM PDT 24
Finished May 07 01:24:46 PM PDT 24
Peak memory 205324 kb
Host smart-23a2f0f9-50bb-4c1f-aac3-2e5f753bc23b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397828441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2397828441
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3713338756
Short name T678
Test name
Test status
Simulation time 13970510 ps
CPU time 0.76 seconds
Started May 07 01:24:43 PM PDT 24
Finished May 07 01:24:46 PM PDT 24
Peak memory 206128 kb
Host smart-8dd0ef57-b91d-4bbf-972c-d99eb129b96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713338756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3713338756
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.648010526
Short name T13
Test name
Test status
Simulation time 1306882312 ps
CPU time 20.23 seconds
Started May 07 01:24:42 PM PDT 24
Finished May 07 01:25:03 PM PDT 24
Peak memory 237328 kb
Host smart-2b9e18f7-372c-4af6-9d97-a235c410299f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648010526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.648010526
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1054890240
Short name T672
Test name
Test status
Simulation time 147648010 ps
CPU time 3.26 seconds
Started May 07 01:24:44 PM PDT 24
Finished May 07 01:24:50 PM PDT 24
Peak memory 219644 kb
Host smart-00df0455-c418-4791-b717-3248dcf25e55
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1054890240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1054890240
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.306945896
Short name T486
Test name
Test status
Simulation time 1643390374 ps
CPU time 9.33 seconds
Started May 07 01:24:40 PM PDT 24
Finished May 07 01:24:51 PM PDT 24
Peak memory 216048 kb
Host smart-91550e6d-adba-4ec7-b21b-3cbfe0859734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306945896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.306945896
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3185537807
Short name T560
Test name
Test status
Simulation time 157221013 ps
CPU time 1.26 seconds
Started May 07 01:24:41 PM PDT 24
Finished May 07 01:24:43 PM PDT 24
Peak memory 207620 kb
Host smart-5775d8f0-e3ad-4536-9074-375ed0cdbad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185537807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3185537807
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2943903615
Short name T530
Test name
Test status
Simulation time 22634997 ps
CPU time 0.76 seconds
Started May 07 01:24:50 PM PDT 24
Finished May 07 01:24:52 PM PDT 24
Peak memory 205448 kb
Host smart-35de65fa-3cf2-4349-9923-03cae205bb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943903615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2943903615
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2848896961
Short name T28
Test name
Test status
Simulation time 1426905000 ps
CPU time 6.02 seconds
Started May 07 01:24:46 PM PDT 24
Finished May 07 01:24:54 PM PDT 24
Peak memory 221876 kb
Host smart-08aeb515-2ed7-45ab-9093-5f616f98ec58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848896961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2848896961
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3091898066
Short name T2
Test name
Test status
Simulation time 44746875 ps
CPU time 0.7 seconds
Started May 07 01:24:49 PM PDT 24
Finished May 07 01:24:51 PM PDT 24
Peak memory 204368 kb
Host smart-14c3b9a5-d267-4f49-b7b2-9c38eaceadcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091898066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3091898066
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1502294420
Short name T706
Test name
Test status
Simulation time 1595161438 ps
CPU time 16.05 seconds
Started May 07 01:24:46 PM PDT 24
Finished May 07 01:25:04 PM PDT 24
Peak memory 223520 kb
Host smart-36d38c6a-e27b-4b9d-9b8c-4932418e941e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502294420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1502294420
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.554326600
Short name T497
Test name
Test status
Simulation time 19519620 ps
CPU time 0.76 seconds
Started May 07 01:24:50 PM PDT 24
Finished May 07 01:24:52 PM PDT 24
Peak memory 205420 kb
Host smart-873af8d9-c07f-4462-9f87-8cf687fd49b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554326600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.554326600
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1675583773
Short name T660
Test name
Test status
Simulation time 4575839903 ps
CPU time 61.67 seconds
Started May 07 01:24:56 PM PDT 24
Finished May 07 01:25:59 PM PDT 24
Peak memory 253332 kb
Host smart-343e8d73-b2da-4b95-b4d1-cced0e6c921e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675583773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1675583773
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.924749781
Short name T119
Test name
Test status
Simulation time 1964059595 ps
CPU time 6.52 seconds
Started May 07 01:24:40 PM PDT 24
Finished May 07 01:24:47 PM PDT 24
Peak memory 218276 kb
Host smart-bc7fa2fe-53e0-4c25-95c4-dd4db3238cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924749781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.924749781
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1320518781
Short name T523
Test name
Test status
Simulation time 221061424 ps
CPU time 4.44 seconds
Started May 07 01:24:43 PM PDT 24
Finished May 07 01:24:49 PM PDT 24
Peak memory 220004 kb
Host smart-7d0ab5f1-0fe6-473f-8a6f-262e08bb02e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1320518781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1320518781
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.1257448920
Short name T643
Test name
Test status
Simulation time 1028678519 ps
CPU time 7.11 seconds
Started May 07 01:24:44 PM PDT 24
Finished May 07 01:24:53 PM PDT 24
Peak memory 216148 kb
Host smart-6e25f177-40b0-4563-99a1-c7a5f232c700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257448920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1257448920
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2026424446
Short name T582
Test name
Test status
Simulation time 1252812843 ps
CPU time 7.73 seconds
Started May 07 01:24:42 PM PDT 24
Finished May 07 01:24:51 PM PDT 24
Peak memory 216036 kb
Host smart-34e8610c-419b-4fee-b3c6-bca6b4c0edfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026424446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2026424446
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1960020664
Short name T570
Test name
Test status
Simulation time 419306117 ps
CPU time 0.83 seconds
Started May 07 01:24:53 PM PDT 24
Finished May 07 01:24:55 PM PDT 24
Peak memory 206184 kb
Host smart-4c595ec5-1297-4e64-bc7f-f679f4ca8dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960020664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1960020664
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1036608152
Short name T608
Test name
Test status
Simulation time 18313174 ps
CPU time 0.75 seconds
Started May 07 01:24:47 PM PDT 24
Finished May 07 01:24:49 PM PDT 24
Peak memory 205340 kb
Host smart-0d73f4dc-e3cf-40c7-b2d7-a00a4c74114b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036608152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1036608152
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1537610308
Short name T182
Test name
Test status
Simulation time 2404664112 ps
CPU time 4.64 seconds
Started May 07 01:24:42 PM PDT 24
Finished May 07 01:24:48 PM PDT 24
Peak memory 218688 kb
Host smart-b3808352-1303-4de8-a2f7-5d208d9639da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537610308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1537610308
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2788968092
Short name T673
Test name
Test status
Simulation time 59325427 ps
CPU time 0.79 seconds
Started May 07 01:24:54 PM PDT 24
Finished May 07 01:24:56 PM PDT 24
Peak memory 204944 kb
Host smart-43fd88fd-a58b-4247-9f2e-03d44456bc86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788968092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2788968092
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.885684366
Short name T257
Test name
Test status
Simulation time 1646312960 ps
CPU time 10.34 seconds
Started May 07 01:24:52 PM PDT 24
Finished May 07 01:25:03 PM PDT 24
Peak memory 222968 kb
Host smart-efbcd78b-e3cc-4373-b948-c2fb1c69981b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885684366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.885684366
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1163985091
Short name T676
Test name
Test status
Simulation time 28508293 ps
CPU time 0.79 seconds
Started May 07 01:24:45 PM PDT 24
Finished May 07 01:24:48 PM PDT 24
Peak memory 206356 kb
Host smart-303c49c7-1664-470e-af55-2221f05c40f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163985091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1163985091
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2413874750
Short name T308
Test name
Test status
Simulation time 1073032585 ps
CPU time 21.98 seconds
Started May 07 01:24:46 PM PDT 24
Finished May 07 01:25:10 PM PDT 24
Peak memory 233796 kb
Host smart-ec855c66-c304-4e65-b4f1-daf1760216e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413874750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2413874750
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.338878273
Short name T198
Test name
Test status
Simulation time 315324814 ps
CPU time 5.22 seconds
Started May 07 01:24:44 PM PDT 24
Finished May 07 01:24:51 PM PDT 24
Peak memory 223916 kb
Host smart-7d9bd24c-442a-4aee-a338-deb3f89e80c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338878273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.338878273
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2426134970
Short name T184
Test name
Test status
Simulation time 3960845059 ps
CPU time 40.09 seconds
Started May 07 01:24:53 PM PDT 24
Finished May 07 01:25:34 PM PDT 24
Peak memory 232872 kb
Host smart-168b4c5b-b81b-45ff-b636-a1eb75e36c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426134970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2426134970
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2198682735
Short name T343
Test name
Test status
Simulation time 1040943660 ps
CPU time 4.82 seconds
Started May 07 01:25:02 PM PDT 24
Finished May 07 01:25:08 PM PDT 24
Peak memory 222028 kb
Host smart-6d94e52b-53a1-4c76-945e-64670f32831d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198682735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2198682735
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.2586920344
Short name T510
Test name
Test status
Simulation time 1493364733 ps
CPU time 13.09 seconds
Started May 07 01:24:54 PM PDT 24
Finished May 07 01:25:09 PM PDT 24
Peak memory 221436 kb
Host smart-bcade8d9-24d9-4f5e-a7f2-d5d76088f7de
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2586920344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.2586920344
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1593825099
Short name T101
Test name
Test status
Simulation time 4295231430 ps
CPU time 19.51 seconds
Started May 07 01:24:47 PM PDT 24
Finished May 07 01:25:08 PM PDT 24
Peak memory 216184 kb
Host smart-fb79c90e-8a86-4b3d-ab23-db5886a44a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593825099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1593825099
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2670669462
Short name T452
Test name
Test status
Simulation time 6005612635 ps
CPU time 8.63 seconds
Started May 07 01:25:02 PM PDT 24
Finished May 07 01:25:12 PM PDT 24
Peak memory 215824 kb
Host smart-fc62f7b5-3ba3-4847-abb8-0c456c66fe4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670669462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2670669462
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.4241678361
Short name T536
Test name
Test status
Simulation time 112072253 ps
CPU time 3.32 seconds
Started May 07 01:24:46 PM PDT 24
Finished May 07 01:24:51 PM PDT 24
Peak memory 216068 kb
Host smart-a1947923-754e-4836-bc6e-f6c7a89494f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241678361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.4241678361
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2207353490
Short name T473
Test name
Test status
Simulation time 67153247 ps
CPU time 0.72 seconds
Started May 07 01:24:43 PM PDT 24
Finished May 07 01:24:46 PM PDT 24
Peak memory 205372 kb
Host smart-fef7ca5b-dba0-4034-8312-5c15751a5308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207353490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2207353490
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.982690110
Short name T732
Test name
Test status
Simulation time 38424900 ps
CPU time 0.72 seconds
Started May 07 01:23:21 PM PDT 24
Finished May 07 01:23:23 PM PDT 24
Peak memory 205312 kb
Host smart-80f716a8-3b07-40fe-b74c-085362c3fff2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982690110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.982690110
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.12572300
Short name T310
Test name
Test status
Simulation time 1355736112 ps
CPU time 5.37 seconds
Started May 07 01:23:30 PM PDT 24
Finished May 07 01:23:37 PM PDT 24
Peak memory 222988 kb
Host smart-ff38379a-9260-4a72-b789-c35983492aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12572300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.12572300
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3383755234
Short name T562
Test name
Test status
Simulation time 62224199 ps
CPU time 0.8 seconds
Started May 07 01:23:21 PM PDT 24
Finished May 07 01:23:23 PM PDT 24
Peak memory 206116 kb
Host smart-11863fb9-0333-4e5f-97e0-aa22a4383292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383755234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3383755234
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1330125668
Short name T302
Test name
Test status
Simulation time 568275596 ps
CPU time 10.13 seconds
Started May 07 01:23:31 PM PDT 24
Finished May 07 01:23:43 PM PDT 24
Peak memory 248908 kb
Host smart-7d84e256-5b5c-4ce7-b80d-3dafd3bdc20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330125668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1330125668
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.725042016
Short name T378
Test name
Test status
Simulation time 345345761 ps
CPU time 7.26 seconds
Started May 07 01:23:29 PM PDT 24
Finished May 07 01:23:37 PM PDT 24
Peak memory 233884 kb
Host smart-12eac06c-156c-4e40-ac5e-2efb0e4254f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725042016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.725042016
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.3659430242
Short name T604
Test name
Test status
Simulation time 109073691 ps
CPU time 1 seconds
Started May 07 01:23:24 PM PDT 24
Finished May 07 01:23:26 PM PDT 24
Peak memory 217736 kb
Host smart-cdde5e02-bf8b-46c2-aaf7-23c80b421337
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659430242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.3659430242
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2054435670
Short name T685
Test name
Test status
Simulation time 5585262698 ps
CPU time 22.95 seconds
Started May 07 01:23:24 PM PDT 24
Finished May 07 01:23:48 PM PDT 24
Peak memory 234592 kb
Host smart-1a8d6d89-a7f6-4f8c-9f88-5ea9e6970583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054435670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2054435670
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3962909545
Short name T159
Test name
Test status
Simulation time 1706185565 ps
CPU time 10.49 seconds
Started May 07 01:23:30 PM PDT 24
Finished May 07 01:23:42 PM PDT 24
Peak memory 220180 kb
Host smart-b86287b5-5871-4f69-8759-a3bef9897436
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3962909545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3962909545
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.436370175
Short name T53
Test name
Test status
Simulation time 102967762 ps
CPU time 1.11 seconds
Started May 07 01:23:15 PM PDT 24
Finished May 07 01:23:17 PM PDT 24
Peak memory 234908 kb
Host smart-b17ddc51-fce1-419f-a3cd-90081ce9cef4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436370175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.436370175
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.4100865390
Short name T388
Test name
Test status
Simulation time 10204959378 ps
CPU time 20.29 seconds
Started May 07 01:23:15 PM PDT 24
Finished May 07 01:23:36 PM PDT 24
Peak memory 216132 kb
Host smart-d7fd9d63-1796-4328-9c1d-9fa92d3d36fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100865390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.4100865390
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3782974408
Short name T632
Test name
Test status
Simulation time 1184916816 ps
CPU time 4.98 seconds
Started May 07 01:23:11 PM PDT 24
Finished May 07 01:23:17 PM PDT 24
Peak memory 216032 kb
Host smart-85793ef2-0367-4b8e-aa78-2a025fe8572c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782974408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3782974408
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2063464954
Short name T693
Test name
Test status
Simulation time 257387686 ps
CPU time 1.3 seconds
Started May 07 01:23:24 PM PDT 24
Finished May 07 01:23:26 PM PDT 24
Peak memory 216132 kb
Host smart-24895f0d-13e5-4a6f-8105-5ce0e4d0bc30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063464954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2063464954
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3634281894
Short name T557
Test name
Test status
Simulation time 88207331 ps
CPU time 0.79 seconds
Started May 07 01:23:22 PM PDT 24
Finished May 07 01:23:24 PM PDT 24
Peak memory 205328 kb
Host smart-4465b91b-7f5b-4573-ae5b-5158e864165a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634281894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3634281894
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.1481855970
Short name T201
Test name
Test status
Simulation time 2833164948 ps
CPU time 10 seconds
Started May 07 01:23:33 PM PDT 24
Finished May 07 01:23:44 PM PDT 24
Peak memory 216188 kb
Host smart-d18fd4cc-b924-433d-82ce-9d8bb91b357b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481855970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1481855970
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1272843828
Short name T707
Test name
Test status
Simulation time 24955402 ps
CPU time 0.7 seconds
Started May 07 01:25:05 PM PDT 24
Finished May 07 01:25:08 PM PDT 24
Peak memory 204076 kb
Host smart-3f148b1c-a8ea-4f1f-81af-d1c142721c09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272843828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1272843828
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.4054325612
Short name T602
Test name
Test status
Simulation time 73647523 ps
CPU time 0.91 seconds
Started May 07 01:24:48 PM PDT 24
Finished May 07 01:24:51 PM PDT 24
Peak memory 206144 kb
Host smart-73b3d604-5eec-492a-8f94-01a9b8e9d21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054325612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.4054325612
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.1154227873
Short name T367
Test name
Test status
Simulation time 8373701890 ps
CPU time 32.85 seconds
Started May 07 01:24:45 PM PDT 24
Finished May 07 01:25:20 PM PDT 24
Peak memory 234344 kb
Host smart-aba8c5da-e9f1-468b-ab1e-f4fd22b59318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154227873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1154227873
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3755090625
Short name T330
Test name
Test status
Simulation time 1534912328 ps
CPU time 19.73 seconds
Started May 07 01:24:47 PM PDT 24
Finished May 07 01:25:08 PM PDT 24
Peak memory 220472 kb
Host smart-07956f28-7fa3-4384-aa16-34cdd6d4c200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755090625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3755090625
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.673270206
Short name T504
Test name
Test status
Simulation time 64668552 ps
CPU time 2.66 seconds
Started May 07 01:24:44 PM PDT 24
Finished May 07 01:24:48 PM PDT 24
Peak memory 223768 kb
Host smart-327bbc78-c4e0-4f71-850a-902eff438a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673270206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.673270206
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3833974462
Short name T214
Test name
Test status
Simulation time 751105916 ps
CPU time 6.18 seconds
Started May 07 01:24:58 PM PDT 24
Finished May 07 01:25:05 PM PDT 24
Peak memory 221928 kb
Host smart-050c3945-5529-41d0-bc27-9c6f53e21655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833974462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3833974462
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2525214108
Short name T210
Test name
Test status
Simulation time 1425605039 ps
CPU time 8 seconds
Started May 07 01:24:56 PM PDT 24
Finished May 07 01:25:06 PM PDT 24
Peak memory 226652 kb
Host smart-9b3762d3-a175-4e3c-9c5c-d837322165c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525214108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2525214108
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2220964485
Short name T520
Test name
Test status
Simulation time 468324243 ps
CPU time 5.44 seconds
Started May 07 01:24:43 PM PDT 24
Finished May 07 01:24:50 PM PDT 24
Peak memory 221340 kb
Host smart-fad916ce-6eec-4d19-b679-3c24ced18208
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2220964485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2220964485
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3489503843
Short name T729
Test name
Test status
Simulation time 624741343 ps
CPU time 8.26 seconds
Started May 07 01:24:46 PM PDT 24
Finished May 07 01:24:56 PM PDT 24
Peak memory 216088 kb
Host smart-a42eaed6-01ee-4f60-80e4-6a1aad3e8079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489503843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3489503843
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3380348466
Short name T433
Test name
Test status
Simulation time 11587638337 ps
CPU time 11.12 seconds
Started May 07 01:24:54 PM PDT 24
Finished May 07 01:25:07 PM PDT 24
Peak memory 216084 kb
Host smart-927f63d7-aefb-4146-85a7-12a9e0a244f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380348466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3380348466
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.459256297
Short name T422
Test name
Test status
Simulation time 259569033 ps
CPU time 1.58 seconds
Started May 07 01:24:44 PM PDT 24
Finished May 07 01:24:48 PM PDT 24
Peak memory 216108 kb
Host smart-e16ec2d4-ca7a-4459-986a-d6ebed3dedc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459256297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.459256297
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3103791552
Short name T516
Test name
Test status
Simulation time 25187408 ps
CPU time 0.79 seconds
Started May 07 01:24:44 PM PDT 24
Finished May 07 01:24:46 PM PDT 24
Peak memory 205432 kb
Host smart-218ac52a-83a6-4701-8fa9-788b52917afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103791552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3103791552
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3663216012
Short name T428
Test name
Test status
Simulation time 17046242 ps
CPU time 0.78 seconds
Started May 07 01:24:51 PM PDT 24
Finished May 07 01:24:53 PM PDT 24
Peak memory 205320 kb
Host smart-818c0a02-5423-4648-9a76-e716e78b2600
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663216012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3663216012
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2909099243
Short name T464
Test name
Test status
Simulation time 43542088 ps
CPU time 0.81 seconds
Started May 07 01:24:57 PM PDT 24
Finished May 07 01:24:59 PM PDT 24
Peak memory 206460 kb
Host smart-e5074358-a07d-4c4f-aa6a-02918255f8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909099243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2909099243
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1238429911
Short name T306
Test name
Test status
Simulation time 928885790 ps
CPU time 22.75 seconds
Started May 07 01:24:43 PM PDT 24
Finished May 07 01:25:08 PM PDT 24
Peak memory 232484 kb
Host smart-ed47bbf4-b668-4fd8-af0c-306e3163e895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238429911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1238429911
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2508503281
Short name T115
Test name
Test status
Simulation time 13302325368 ps
CPU time 140.93 seconds
Started May 07 01:24:45 PM PDT 24
Finished May 07 01:27:08 PM PDT 24
Peak memory 227404 kb
Host smart-97bd6b04-e8ef-4b7d-b78f-c4d7ef063336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508503281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2508503281
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.849392669
Short name T337
Test name
Test status
Simulation time 720699393 ps
CPU time 9.48 seconds
Started May 07 01:24:49 PM PDT 24
Finished May 07 01:25:00 PM PDT 24
Peak memory 221848 kb
Host smart-1a3cd97b-8983-4277-8aa1-208aa1d43cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849392669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.849392669
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.22756942
Short name T598
Test name
Test status
Simulation time 551616105 ps
CPU time 3.63 seconds
Started May 07 01:24:57 PM PDT 24
Finished May 07 01:25:02 PM PDT 24
Peak memory 221908 kb
Host smart-ac99d389-d7a2-4549-b59a-30586530db67
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=22756942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_direc
t.22756942
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2968086948
Short name T35
Test name
Test status
Simulation time 57910563 ps
CPU time 1.14 seconds
Started May 07 01:25:02 PM PDT 24
Finished May 07 01:25:04 PM PDT 24
Peak memory 206608 kb
Host smart-02d44ce8-6aa8-403a-b5b5-d236bfd1f0e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968086948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2968086948
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.109256072
Short name T99
Test name
Test status
Simulation time 19599968254 ps
CPU time 49.47 seconds
Started May 07 01:24:55 PM PDT 24
Finished May 07 01:25:46 PM PDT 24
Peak memory 216192 kb
Host smart-11542986-8baa-4a22-8fbd-4b1abd20137a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109256072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.109256072
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3102770515
Short name T16
Test name
Test status
Simulation time 40048481901 ps
CPU time 17.6 seconds
Started May 07 01:24:50 PM PDT 24
Finished May 07 01:25:09 PM PDT 24
Peak memory 216164 kb
Host smart-51083644-2cea-407a-9620-0fc6edb4ae46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102770515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3102770515
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3283896983
Short name T722
Test name
Test status
Simulation time 235362994 ps
CPU time 2.85 seconds
Started May 07 01:25:01 PM PDT 24
Finished May 07 01:25:05 PM PDT 24
Peak memory 216204 kb
Host smart-6abcb212-9296-44aa-84a7-4a03152140b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283896983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3283896983
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.350818011
Short name T701
Test name
Test status
Simulation time 170757074 ps
CPU time 0.85 seconds
Started May 07 01:24:49 PM PDT 24
Finished May 07 01:24:51 PM PDT 24
Peak memory 206432 kb
Host smart-34b7163a-bf8a-47c3-be06-96102057dbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350818011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.350818011
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1216525525
Short name T512
Test name
Test status
Simulation time 29905607 ps
CPU time 0.7 seconds
Started May 07 01:25:05 PM PDT 24
Finished May 07 01:25:07 PM PDT 24
Peak memory 204352 kb
Host smart-6a4f9e53-98e0-4bfc-8773-e7418e13ffa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216525525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1216525525
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3647480052
Short name T26
Test name
Test status
Simulation time 728613447 ps
CPU time 2.72 seconds
Started May 07 01:25:03 PM PDT 24
Finished May 07 01:25:07 PM PDT 24
Peak memory 222852 kb
Host smart-8ac45c20-979f-4912-9eb3-6044ac328d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647480052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3647480052
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3188800497
Short name T607
Test name
Test status
Simulation time 25634125 ps
CPU time 0.74 seconds
Started May 07 01:24:55 PM PDT 24
Finished May 07 01:24:57 PM PDT 24
Peak memory 206436 kb
Host smart-588c58fd-e395-47f0-bbd8-ce3de5b1e75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188800497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3188800497
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1563063440
Short name T357
Test name
Test status
Simulation time 11358788801 ps
CPU time 76.99 seconds
Started May 07 01:24:46 PM PDT 24
Finished May 07 01:26:05 PM PDT 24
Peak memory 234600 kb
Host smart-b6632e65-a2bb-47c2-90ef-7949d23b2a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563063440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1563063440
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2167187049
Short name T341
Test name
Test status
Simulation time 10766002631 ps
CPU time 10.04 seconds
Started May 07 01:24:59 PM PDT 24
Finished May 07 01:25:10 PM PDT 24
Peak memory 222924 kb
Host smart-7b4d6324-50ee-4240-9eef-ebb0f6043e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167187049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2167187049
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3339126772
Short name T547
Test name
Test status
Simulation time 1083781992 ps
CPU time 4.57 seconds
Started May 07 01:24:57 PM PDT 24
Finished May 07 01:25:02 PM PDT 24
Peak memory 219728 kb
Host smart-110edb27-5398-47d3-85cc-eb5a9c0aecce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3339126772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3339126772
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2588245709
Short name T681
Test name
Test status
Simulation time 2402094235 ps
CPU time 2.67 seconds
Started May 07 01:24:53 PM PDT 24
Finished May 07 01:24:57 PM PDT 24
Peak memory 216172 kb
Host smart-7d1886a0-a385-4d19-a0eb-8c28354db370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588245709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2588245709
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3503694434
Short name T476
Test name
Test status
Simulation time 33117562353 ps
CPU time 24.92 seconds
Started May 07 01:25:05 PM PDT 24
Finished May 07 01:25:32 PM PDT 24
Peak memory 215960 kb
Host smart-a5c70ee3-9753-4c0e-8172-255314984246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503694434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3503694434
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3659433865
Short name T400
Test name
Test status
Simulation time 52139670 ps
CPU time 1.63 seconds
Started May 07 01:24:51 PM PDT 24
Finished May 07 01:24:54 PM PDT 24
Peak memory 216104 kb
Host smart-15f41294-8368-491e-894c-50f192e42a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659433865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3659433865
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3690386364
Short name T731
Test name
Test status
Simulation time 39599422 ps
CPU time 0.9 seconds
Started May 07 01:24:48 PM PDT 24
Finished May 07 01:24:51 PM PDT 24
Peak memory 206564 kb
Host smart-75b429a7-dd6d-441f-bff6-8a53685f3d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690386364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3690386364
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1397937127
Short name T371
Test name
Test status
Simulation time 603457898 ps
CPU time 5.36 seconds
Started May 07 01:25:02 PM PDT 24
Finished May 07 01:25:08 PM PDT 24
Peak memory 221844 kb
Host smart-8bc02ce2-ac3e-42ca-967e-e81100991939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397937127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1397937127
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.4036373246
Short name T652
Test name
Test status
Simulation time 66953947 ps
CPU time 0.77 seconds
Started May 07 01:24:54 PM PDT 24
Finished May 07 01:24:56 PM PDT 24
Peak memory 204984 kb
Host smart-628c6080-d6ff-4943-b3fb-cc58f6e14f94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036373246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
4036373246
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1042544286
Short name T705
Test name
Test status
Simulation time 188381061 ps
CPU time 0.75 seconds
Started May 07 01:24:51 PM PDT 24
Finished May 07 01:24:53 PM PDT 24
Peak memory 206448 kb
Host smart-34c3ce46-c0a2-4dc5-9332-1f34ba25e780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042544286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1042544286
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3771873715
Short name T728
Test name
Test status
Simulation time 490335760 ps
CPU time 17.87 seconds
Started May 07 01:25:03 PM PDT 24
Finished May 07 01:25:21 PM PDT 24
Peak memory 239640 kb
Host smart-919d2436-f992-435b-92e3-65139d835f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771873715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3771873715
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.983621414
Short name T345
Test name
Test status
Simulation time 356156757 ps
CPU time 7.37 seconds
Started May 07 01:24:51 PM PDT 24
Finished May 07 01:24:59 PM PDT 24
Peak memory 224188 kb
Host smart-e90e7817-9927-4d9d-9fb5-03f1c8b2a5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983621414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.983621414
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3307604675
Short name T319
Test name
Test status
Simulation time 1288913508 ps
CPU time 8.65 seconds
Started May 07 01:25:10 PM PDT 24
Finished May 07 01:25:20 PM PDT 24
Peak memory 223168 kb
Host smart-28f6cf93-a394-4383-8c7c-85034d187916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307604675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3307604675
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1325865645
Short name T593
Test name
Test status
Simulation time 2420704592 ps
CPU time 17.61 seconds
Started May 07 01:25:04 PM PDT 24
Finished May 07 01:25:23 PM PDT 24
Peak memory 218988 kb
Host smart-91fadc0b-acdf-458b-bd42-f569b3536fe8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1325865645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1325865645
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2123605506
Short name T391
Test name
Test status
Simulation time 32844009495 ps
CPU time 47.82 seconds
Started May 07 01:24:57 PM PDT 24
Finished May 07 01:25:46 PM PDT 24
Peak memory 216176 kb
Host smart-559c4ad4-e94b-4e99-bb7e-85cb84cbd518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123605506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2123605506
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2862428201
Short name T448
Test name
Test status
Simulation time 5485781276 ps
CPU time 4.55 seconds
Started May 07 01:24:53 PM PDT 24
Finished May 07 01:24:59 PM PDT 24
Peak memory 216036 kb
Host smart-2d1b83a5-c3fc-4841-9a3a-da79a57c4b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862428201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2862428201
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3137375082
Short name T702
Test name
Test status
Simulation time 225918909 ps
CPU time 2.32 seconds
Started May 07 01:24:57 PM PDT 24
Finished May 07 01:25:01 PM PDT 24
Peak memory 216080 kb
Host smart-afdc00cb-3a7a-406b-bbeb-d01e83601bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137375082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3137375082
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1731653956
Short name T541
Test name
Test status
Simulation time 62280228 ps
CPU time 0.71 seconds
Started May 07 01:24:54 PM PDT 24
Finished May 07 01:24:55 PM PDT 24
Peak memory 205464 kb
Host smart-41284df8-95b3-451f-8e03-9c48d4be9257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731653956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1731653956
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.454701787
Short name T440
Test name
Test status
Simulation time 12850022 ps
CPU time 0.73 seconds
Started May 07 01:24:57 PM PDT 24
Finished May 07 01:24:59 PM PDT 24
Peak memory 205132 kb
Host smart-a63d2289-5464-4f4f-8506-36f14993013c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454701787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.454701787
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3042820857
Short name T190
Test name
Test status
Simulation time 1696663835 ps
CPU time 20.78 seconds
Started May 07 01:24:51 PM PDT 24
Finished May 07 01:25:13 PM PDT 24
Peak memory 218344 kb
Host smart-308b52d4-6fcf-46b6-a500-a1ff519f5be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042820857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3042820857
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2158193487
Short name T659
Test name
Test status
Simulation time 26735579 ps
CPU time 0.74 seconds
Started May 07 01:25:00 PM PDT 24
Finished May 07 01:25:02 PM PDT 24
Peak memory 205400 kb
Host smart-e91fd429-5989-46cc-a9e4-3fdad366282b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158193487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2158193487
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2350071791
Short name T6
Test name
Test status
Simulation time 330730178 ps
CPU time 5.12 seconds
Started May 07 01:24:53 PM PDT 24
Finished May 07 01:24:59 PM PDT 24
Peak memory 222136 kb
Host smart-30321c54-37e6-4311-ac56-f8ac23411a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350071791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2350071791
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.505912368
Short name T642
Test name
Test status
Simulation time 107131243 ps
CPU time 2.67 seconds
Started May 07 01:24:51 PM PDT 24
Finished May 07 01:24:55 PM PDT 24
Peak memory 218216 kb
Host smart-fcc055bd-6447-4fb9-81ef-4fa5cc6c4cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505912368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.505912368
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.960403999
Short name T263
Test name
Test status
Simulation time 3574531775 ps
CPU time 5.51 seconds
Started May 07 01:24:48 PM PDT 24
Finished May 07 01:24:55 PM PDT 24
Peak memory 222628 kb
Host smart-da05e4f3-d04b-49a0-a519-3c7dddfc3c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960403999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.960403999
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.263347686
Short name T548
Test name
Test status
Simulation time 327435797 ps
CPU time 3.92 seconds
Started May 07 01:25:02 PM PDT 24
Finished May 07 01:25:06 PM PDT 24
Peak memory 222712 kb
Host smart-fe1fc9bd-3c22-4933-aecc-3e3e12bd5404
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=263347686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.263347686
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.264693647
Short name T384
Test name
Test status
Simulation time 10532318565 ps
CPU time 55.62 seconds
Started May 07 01:24:53 PM PDT 24
Finished May 07 01:25:50 PM PDT 24
Peak memory 216320 kb
Host smart-3e0ec83c-f917-4d9b-a5fe-633d5e7b26d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264693647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.264693647
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3799482589
Short name T662
Test name
Test status
Simulation time 1410998420 ps
CPU time 5.59 seconds
Started May 07 01:24:51 PM PDT 24
Finished May 07 01:24:58 PM PDT 24
Peak memory 215976 kb
Host smart-b521c12c-7e7f-459e-b7ed-deda5245c616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799482589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3799482589
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1144164462
Short name T409
Test name
Test status
Simulation time 227877032 ps
CPU time 1.74 seconds
Started May 07 01:24:58 PM PDT 24
Finished May 07 01:25:00 PM PDT 24
Peak memory 216076 kb
Host smart-a4c3d405-a533-4f52-ad9a-ec51b6a9cbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144164462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1144164462
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2833614246
Short name T587
Test name
Test status
Simulation time 430815400 ps
CPU time 1.05 seconds
Started May 07 01:24:54 PM PDT 24
Finished May 07 01:24:56 PM PDT 24
Peak memory 206476 kb
Host smart-a684363d-7dad-4961-a5e0-fa39eda8cd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833614246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2833614246
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.202028268
Short name T458
Test name
Test status
Simulation time 15620906 ps
CPU time 0.68 seconds
Started May 07 01:25:06 PM PDT 24
Finished May 07 01:25:09 PM PDT 24
Peak memory 205344 kb
Host smart-45260372-0104-48d6-b7fb-7eff1b5302e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202028268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.202028268
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2723358755
Short name T342
Test name
Test status
Simulation time 478473157 ps
CPU time 3.02 seconds
Started May 07 01:25:10 PM PDT 24
Finished May 07 01:25:14 PM PDT 24
Peak memory 218132 kb
Host smart-0d3de7ec-da37-4016-8314-78a4dfa7deb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723358755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2723358755
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.446607969
Short name T461
Test name
Test status
Simulation time 16253887 ps
CPU time 0.75 seconds
Started May 07 01:25:12 PM PDT 24
Finished May 07 01:25:14 PM PDT 24
Peak memory 204996 kb
Host smart-33759cf7-1d78-4cad-a10c-49028de73411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446607969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.446607969
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2871770832
Short name T301
Test name
Test status
Simulation time 1149351925 ps
CPU time 18.94 seconds
Started May 07 01:25:08 PM PDT 24
Finished May 07 01:25:29 PM PDT 24
Peak memory 236492 kb
Host smart-256a7f2b-8d3f-4738-9f1f-88910a19fdd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871770832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2871770832
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.451134357
Short name T354
Test name
Test status
Simulation time 15686074413 ps
CPU time 10.7 seconds
Started May 07 01:25:18 PM PDT 24
Finished May 07 01:25:31 PM PDT 24
Peak memory 232620 kb
Host smart-bb4eb6dc-0877-470f-99dd-3fc04a39490d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451134357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.451134357
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.3473303920
Short name T312
Test name
Test status
Simulation time 2599111400 ps
CPU time 4.38 seconds
Started May 07 01:24:58 PM PDT 24
Finished May 07 01:25:04 PM PDT 24
Peak memory 216680 kb
Host smart-5bbb4ea7-54f9-4fc3-8a82-ff18307b8aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473303920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3473303920
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3685655584
Short name T498
Test name
Test status
Simulation time 1474532407 ps
CPU time 11.62 seconds
Started May 07 01:24:59 PM PDT 24
Finished May 07 01:25:12 PM PDT 24
Peak memory 219568 kb
Host smart-6efd9aa2-2ee9-4a53-92b6-01d25e01780d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3685655584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3685655584
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.2707077049
Short name T404
Test name
Test status
Simulation time 2322323709 ps
CPU time 19.5 seconds
Started May 07 01:24:58 PM PDT 24
Finished May 07 01:25:19 PM PDT 24
Peak memory 216144 kb
Host smart-c5d8c9c9-9d75-486d-88eb-1f4fca2f1ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707077049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2707077049
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2664770483
Short name T18
Test name
Test status
Simulation time 51827461299 ps
CPU time 30.82 seconds
Started May 07 01:25:13 PM PDT 24
Finished May 07 01:25:45 PM PDT 24
Peak memory 216112 kb
Host smart-908e073e-04fe-4ba9-81bf-5f2260422981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664770483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2664770483
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.1601646909
Short name T60
Test name
Test status
Simulation time 188402466 ps
CPU time 5.23 seconds
Started May 07 01:24:58 PM PDT 24
Finished May 07 01:25:04 PM PDT 24
Peak memory 216088 kb
Host smart-3e82a264-c136-46a7-99b4-3400bb62f425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601646909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1601646909
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.4140873122
Short name T581
Test name
Test status
Simulation time 66909346 ps
CPU time 0.8 seconds
Started May 07 01:25:01 PM PDT 24
Finished May 07 01:25:03 PM PDT 24
Peak memory 205432 kb
Host smart-04a44fcc-9acb-4846-a6dc-2e5a1c06e26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140873122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.4140873122
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.2185175259
Short name T714
Test name
Test status
Simulation time 12528496 ps
CPU time 0.76 seconds
Started May 07 01:25:06 PM PDT 24
Finished May 07 01:25:08 PM PDT 24
Peak memory 204968 kb
Host smart-869a0e4d-fb3d-4c85-bc3e-955286ffbbc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185175259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
2185175259
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.964536359
Short name T430
Test name
Test status
Simulation time 69143179 ps
CPU time 0.81 seconds
Started May 07 01:25:07 PM PDT 24
Finished May 07 01:25:10 PM PDT 24
Peak memory 206432 kb
Host smart-2285beae-ca25-4b4d-a700-87a6210a5225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964536359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.964536359
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1322971964
Short name T258
Test name
Test status
Simulation time 258195181 ps
CPU time 6.46 seconds
Started May 07 01:25:00 PM PDT 24
Finished May 07 01:25:08 PM PDT 24
Peak memory 218620 kb
Host smart-6f2371ae-2c66-432f-8b1c-34f232b3436c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322971964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1322971964
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.311916839
Short name T603
Test name
Test status
Simulation time 509850755 ps
CPU time 4.12 seconds
Started May 07 01:24:58 PM PDT 24
Finished May 07 01:25:03 PM PDT 24
Peak memory 220508 kb
Host smart-9d6e1b3c-e7ed-4e15-a727-7aacedc9c4e7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=311916839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.311916839
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2525479703
Short name T535
Test name
Test status
Simulation time 1708116519 ps
CPU time 8.3 seconds
Started May 07 01:25:14 PM PDT 24
Finished May 07 01:25:24 PM PDT 24
Peak memory 216044 kb
Host smart-90d39d9e-8872-4eac-b487-78529afa67ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525479703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2525479703
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2909727067
Short name T615
Test name
Test status
Simulation time 186454493 ps
CPU time 3.61 seconds
Started May 07 01:25:07 PM PDT 24
Finished May 07 01:25:13 PM PDT 24
Peak memory 216036 kb
Host smart-ad2a7a0f-ebac-45ca-97ab-809a7e7af5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909727067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2909727067
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1987904104
Short name T717
Test name
Test status
Simulation time 68044027 ps
CPU time 0.99 seconds
Started May 07 01:25:09 PM PDT 24
Finished May 07 01:25:11 PM PDT 24
Peak memory 206420 kb
Host smart-5b3581e5-55d3-409f-93f3-a87f696130ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987904104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1987904104
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1132274633
Short name T675
Test name
Test status
Simulation time 33027302 ps
CPU time 0.73 seconds
Started May 07 01:25:09 PM PDT 24
Finished May 07 01:25:11 PM PDT 24
Peak memory 204364 kb
Host smart-c33ecf0c-dff4-4550-8a21-d2dcc95993b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132274633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1132274633
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3849362634
Short name T426
Test name
Test status
Simulation time 34852435 ps
CPU time 0.82 seconds
Started May 07 01:25:18 PM PDT 24
Finished May 07 01:25:20 PM PDT 24
Peak memory 206180 kb
Host smart-5747f472-23e8-43ab-9711-bd1122e180b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849362634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3849362634
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1852363300
Short name T360
Test name
Test status
Simulation time 4728631196 ps
CPU time 40.27 seconds
Started May 07 01:25:18 PM PDT 24
Finished May 07 01:26:00 PM PDT 24
Peak memory 230668 kb
Host smart-858f6007-ad67-48de-9dea-5feac5990cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852363300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1852363300
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2379437024
Short name T236
Test name
Test status
Simulation time 588143619 ps
CPU time 3.35 seconds
Started May 07 01:25:05 PM PDT 24
Finished May 07 01:25:11 PM PDT 24
Peak memory 216280 kb
Host smart-9a7154c5-f4c9-4796-adf9-c62de249287c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379437024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2379437024
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3402662167
Short name T573
Test name
Test status
Simulation time 980269959 ps
CPU time 7.09 seconds
Started May 07 01:25:07 PM PDT 24
Finished May 07 01:25:16 PM PDT 24
Peak memory 220164 kb
Host smart-e13efbe8-d079-4ddf-8132-3d6263b3de6a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3402662167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3402662167
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1658073145
Short name T395
Test name
Test status
Simulation time 4696851396 ps
CPU time 24.59 seconds
Started May 07 01:25:20 PM PDT 24
Finished May 07 01:25:47 PM PDT 24
Peak memory 216108 kb
Host smart-05d5013c-6319-4ab2-8cea-c6826e7a3df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658073145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1658073145
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2304594819
Short name T566
Test name
Test status
Simulation time 804892575 ps
CPU time 5.95 seconds
Started May 07 01:25:03 PM PDT 24
Finished May 07 01:25:10 PM PDT 24
Peak memory 216028 kb
Host smart-7acd4b8d-bf7a-477e-911c-96c13d2ddbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304594819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2304594819
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2358279511
Short name T417
Test name
Test status
Simulation time 32179600 ps
CPU time 1.51 seconds
Started May 07 01:25:05 PM PDT 24
Finished May 07 01:25:08 PM PDT 24
Peak memory 216060 kb
Host smart-afd24f36-4894-4ce4-8d7e-7506248e99e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358279511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2358279511
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1323677392
Short name T556
Test name
Test status
Simulation time 84147627 ps
CPU time 0.98 seconds
Started May 07 01:25:04 PM PDT 24
Finished May 07 01:25:06 PM PDT 24
Peak memory 206468 kb
Host smart-26700f88-07e5-4543-aac6-5b76c7912aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323677392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1323677392
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.235295459
Short name T585
Test name
Test status
Simulation time 39599211 ps
CPU time 0.69 seconds
Started May 07 01:25:04 PM PDT 24
Finished May 07 01:25:07 PM PDT 24
Peak memory 204368 kb
Host smart-98360796-20ec-4f02-9379-eb87e7dec4a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235295459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.235295459
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3455840179
Short name T513
Test name
Test status
Simulation time 48251902 ps
CPU time 0.78 seconds
Started May 07 01:25:03 PM PDT 24
Finished May 07 01:25:05 PM PDT 24
Peak memory 206452 kb
Host smart-01fe7f8d-8f59-4580-bfbb-b2420db88f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455840179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3455840179
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2162547634
Short name T156
Test name
Test status
Simulation time 9296948347 ps
CPU time 36.95 seconds
Started May 07 01:25:03 PM PDT 24
Finished May 07 01:25:42 PM PDT 24
Peak memory 232576 kb
Host smart-f41f7358-e757-492f-9e29-36af225af94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162547634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2162547634
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.4023045649
Short name T12
Test name
Test status
Simulation time 15613169308 ps
CPU time 17.17 seconds
Started May 07 01:25:14 PM PDT 24
Finished May 07 01:25:32 PM PDT 24
Peak memory 218540 kb
Host smart-c908f372-a69f-4a67-837c-0c104232e090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023045649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.4023045649
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1648634311
Short name T270
Test name
Test status
Simulation time 11571193454 ps
CPU time 9.13 seconds
Started May 07 01:25:15 PM PDT 24
Finished May 07 01:25:25 PM PDT 24
Peak memory 223056 kb
Host smart-19ada0db-b765-4628-bca7-7c941d9eeb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648634311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1648634311
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1375881222
Short name T203
Test name
Test status
Simulation time 4167484510 ps
CPU time 13.73 seconds
Started May 07 01:25:06 PM PDT 24
Finished May 07 01:25:22 PM PDT 24
Peak memory 222680 kb
Host smart-24d39b39-f7b2-4194-b87b-efe15f7f6966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375881222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1375881222
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2884295961
Short name T634
Test name
Test status
Simulation time 221659203 ps
CPU time 4.99 seconds
Started May 07 01:25:16 PM PDT 24
Finished May 07 01:25:22 PM PDT 24
Peak memory 221876 kb
Host smart-f53ca23b-e9fe-4703-b560-37f83e789015
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2884295961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2884295961
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3776857190
Short name T647
Test name
Test status
Simulation time 13471880357 ps
CPU time 25.29 seconds
Started May 07 01:25:13 PM PDT 24
Finished May 07 01:25:40 PM PDT 24
Peak memory 216168 kb
Host smart-8894035a-4e75-47e8-997c-e65df98cef33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776857190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3776857190
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.683674394
Short name T617
Test name
Test status
Simulation time 15885038767 ps
CPU time 24.19 seconds
Started May 07 01:25:06 PM PDT 24
Finished May 07 01:25:32 PM PDT 24
Peak memory 216096 kb
Host smart-f802bde5-81fb-40be-b458-4b105cf440d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683674394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.683674394
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2552711684
Short name T488
Test name
Test status
Simulation time 35616933 ps
CPU time 0.92 seconds
Started May 07 01:25:09 PM PDT 24
Finished May 07 01:25:12 PM PDT 24
Peak memory 207024 kb
Host smart-00e73012-2cb8-4276-8ba7-16337f8263c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552711684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2552711684
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.708805249
Short name T719
Test name
Test status
Simulation time 283210282 ps
CPU time 0.9 seconds
Started May 07 01:25:07 PM PDT 24
Finished May 07 01:25:10 PM PDT 24
Peak memory 205404 kb
Host smart-ba75397b-3ef6-4f85-9106-6925426c9b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708805249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.708805249
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.3168044758
Short name T83
Test name
Test status
Simulation time 208416504 ps
CPU time 2.45 seconds
Started May 07 01:25:06 PM PDT 24
Finished May 07 01:25:10 PM PDT 24
Peak memory 221908 kb
Host smart-f504ddf1-e0c2-4e4a-bac1-652807c7bcd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168044758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3168044758
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3313559155
Short name T517
Test name
Test status
Simulation time 24826693 ps
CPU time 0.68 seconds
Started May 07 01:25:18 PM PDT 24
Finished May 07 01:25:21 PM PDT 24
Peak memory 204984 kb
Host smart-1ee5ae82-b69c-46d4-8eb8-b59267b378a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313559155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3313559155
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3020223993
Short name T441
Test name
Test status
Simulation time 20522648 ps
CPU time 0.79 seconds
Started May 07 01:25:15 PM PDT 24
Finished May 07 01:25:17 PM PDT 24
Peak memory 206500 kb
Host smart-2fcc7b70-3782-4e2b-a376-ba32a97588cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020223993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3020223993
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2994780141
Short name T305
Test name
Test status
Simulation time 3048509007 ps
CPU time 19.66 seconds
Started May 07 01:25:18 PM PDT 24
Finished May 07 01:25:40 PM PDT 24
Peak memory 240756 kb
Host smart-0c692c52-b01f-4945-a8bd-a4cbff71a616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994780141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2994780141
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1695464969
Short name T501
Test name
Test status
Simulation time 1135364172 ps
CPU time 8.5 seconds
Started May 07 01:25:13 PM PDT 24
Finished May 07 01:25:22 PM PDT 24
Peak memory 233980 kb
Host smart-ba66cc9f-0f68-4c7b-9dd5-b2c52f9cf0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695464969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1695464969
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.793844323
Short name T350
Test name
Test status
Simulation time 916369332 ps
CPU time 3.76 seconds
Started May 07 01:25:16 PM PDT 24
Finished May 07 01:25:21 PM PDT 24
Peak memory 219036 kb
Host smart-63ab5685-d651-4a4d-afd4-a4a8ca571504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793844323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.793844323
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2881335188
Short name T277
Test name
Test status
Simulation time 3896282050 ps
CPU time 7.52 seconds
Started May 07 01:25:08 PM PDT 24
Finished May 07 01:25:17 PM PDT 24
Peak memory 233240 kb
Host smart-adbc6801-9a33-45b5-b7bc-3909230006f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881335188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2881335188
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3799119138
Short name T463
Test name
Test status
Simulation time 572491584 ps
CPU time 3.49 seconds
Started May 07 01:25:15 PM PDT 24
Finished May 07 01:25:20 PM PDT 24
Peak memory 218596 kb
Host smart-4313cba3-195b-40e9-b9db-40b857c69a20
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3799119138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3799119138
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.779196521
Short name T403
Test name
Test status
Simulation time 4951399499 ps
CPU time 20.08 seconds
Started May 07 01:25:09 PM PDT 24
Finished May 07 01:25:31 PM PDT 24
Peak memory 216128 kb
Host smart-e3c5891b-a188-4474-a0ae-6c1c87eac032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779196521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.779196521
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3373053676
Short name T653
Test name
Test status
Simulation time 243029529 ps
CPU time 1.34 seconds
Started May 07 01:25:17 PM PDT 24
Finished May 07 01:25:20 PM PDT 24
Peak memory 207504 kb
Host smart-7f276cbd-cbd8-4590-b739-abf50fe32432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373053676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3373053676
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.2067964211
Short name T687
Test name
Test status
Simulation time 18437542 ps
CPU time 0.88 seconds
Started May 07 01:25:04 PM PDT 24
Finished May 07 01:25:06 PM PDT 24
Peak memory 206196 kb
Host smart-d426eba6-84a2-4f5b-9601-096df514b3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067964211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2067964211
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3868264958
Short name T455
Test name
Test status
Simulation time 610246444 ps
CPU time 0.91 seconds
Started May 07 01:25:03 PM PDT 24
Finished May 07 01:25:04 PM PDT 24
Peak memory 205832 kb
Host smart-7346c2ce-055e-4c8f-8135-e894ed949d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868264958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3868264958
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.372216553
Short name T336
Test name
Test status
Simulation time 177458479 ps
CPU time 2.68 seconds
Started May 07 01:25:08 PM PDT 24
Finished May 07 01:25:13 PM PDT 24
Peak memory 222492 kb
Host smart-c585099c-1ef1-48f4-a3c7-970e4afc166e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372216553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.372216553
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.435801370
Short name T429
Test name
Test status
Simulation time 57384758 ps
CPU time 0.74 seconds
Started May 07 01:23:27 PM PDT 24
Finished May 07 01:23:28 PM PDT 24
Peak memory 205028 kb
Host smart-4801d31c-52d8-4b00-aaf6-226c28ab7ee1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435801370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.435801370
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3367684876
Short name T320
Test name
Test status
Simulation time 11959698452 ps
CPU time 24.11 seconds
Started May 07 01:23:13 PM PDT 24
Finished May 07 01:23:38 PM PDT 24
Peak memory 219104 kb
Host smart-bfdbf093-4caa-4c55-8ebb-fff600e54f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367684876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3367684876
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3115425570
Short name T620
Test name
Test status
Simulation time 47703824 ps
CPU time 0.78 seconds
Started May 07 01:23:27 PM PDT 24
Finished May 07 01:23:29 PM PDT 24
Peak memory 206120 kb
Host smart-de875cca-e239-4cf2-8fbf-a642d03404de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115425570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3115425570
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2163739392
Short name T304
Test name
Test status
Simulation time 9788636623 ps
CPU time 34.27 seconds
Started May 07 01:23:33 PM PDT 24
Finished May 07 01:24:09 PM PDT 24
Peak memory 240752 kb
Host smart-811131ec-eda0-4c3f-8e9e-85bd4c6cbe6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163739392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2163739392
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1528811037
Short name T325
Test name
Test status
Simulation time 1320661224 ps
CPU time 4.93 seconds
Started May 07 01:23:29 PM PDT 24
Finished May 07 01:23:34 PM PDT 24
Peak memory 220760 kb
Host smart-3f64773f-72f3-4fd9-bc65-70082ff3cc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528811037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1528811037
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.3472240022
Short name T347
Test name
Test status
Simulation time 1548082999 ps
CPU time 24.35 seconds
Started May 07 01:23:32 PM PDT 24
Finished May 07 01:23:58 PM PDT 24
Peak memory 232312 kb
Host smart-cfd1a40b-165f-4ef7-b4d6-e2ad8e63d70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472240022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3472240022
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.951753055
Short name T616
Test name
Test status
Simulation time 80165551 ps
CPU time 1.01 seconds
Started May 07 01:23:31 PM PDT 24
Finished May 07 01:23:34 PM PDT 24
Peak memory 216516 kb
Host smart-403c523a-3e21-4f02-a6a4-09493c5e413a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951753055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.spi_device_mem_parity.951753055
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3656991835
Short name T294
Test name
Test status
Simulation time 5678493255 ps
CPU time 8.49 seconds
Started May 07 01:23:21 PM PDT 24
Finished May 07 01:23:31 PM PDT 24
Peak memory 233832 kb
Host smart-5493f2e9-33e2-467f-8e52-ca80d49f4a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656991835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3656991835
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1784300203
Short name T186
Test name
Test status
Simulation time 2050154197 ps
CPU time 5.91 seconds
Started May 07 01:23:14 PM PDT 24
Finished May 07 01:23:21 PM PDT 24
Peak memory 222664 kb
Host smart-3186a1f7-dd24-453e-8311-a0178236aae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784300203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1784300203
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.279055089
Short name T533
Test name
Test status
Simulation time 2852383747 ps
CPU time 8.71 seconds
Started May 07 01:23:21 PM PDT 24
Finished May 07 01:23:31 PM PDT 24
Peak memory 218732 kb
Host smart-8a35cf98-a4f5-41ba-a3cb-492f2c8e1ecb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=279055089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.279055089
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2473999067
Short name T738
Test name
Test status
Simulation time 3791720820 ps
CPU time 13.63 seconds
Started May 07 01:23:18 PM PDT 24
Finished May 07 01:23:33 PM PDT 24
Peak memory 216228 kb
Host smart-99437275-3efe-474b-b30d-f03832060026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473999067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2473999067
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.896801904
Short name T169
Test name
Test status
Simulation time 1167625484 ps
CPU time 5.05 seconds
Started May 07 01:23:16 PM PDT 24
Finished May 07 01:23:22 PM PDT 24
Peak memory 216032 kb
Host smart-e6fe0721-10fc-469d-8a04-02ec63c1448d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896801904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.896801904
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.4270561045
Short name T484
Test name
Test status
Simulation time 100734838 ps
CPU time 1.45 seconds
Started May 07 01:23:18 PM PDT 24
Finished May 07 01:23:21 PM PDT 24
Peak memory 216052 kb
Host smart-46e6e90c-1aa1-4490-8489-b45487aeea5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270561045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.4270561045
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3469025905
Short name T665
Test name
Test status
Simulation time 428584730 ps
CPU time 1.16 seconds
Started May 07 01:23:11 PM PDT 24
Finished May 07 01:23:13 PM PDT 24
Peak memory 206476 kb
Host smart-f898f95d-69ab-47bb-a6e0-01fcf0c4ff05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469025905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3469025905
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.1455041102
Short name T47
Test name
Test status
Simulation time 4608701195 ps
CPU time 15.44 seconds
Started May 07 01:23:27 PM PDT 24
Finished May 07 01:23:43 PM PDT 24
Peak memory 216068 kb
Host smart-5eb5aa87-74e4-412f-ba83-805372917fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455041102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1455041102
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2815715050
Short name T490
Test name
Test status
Simulation time 38495762 ps
CPU time 0.72 seconds
Started May 07 01:23:24 PM PDT 24
Finished May 07 01:23:26 PM PDT 24
Peak memory 204972 kb
Host smart-b05edad9-964a-4570-808c-353627b6a75b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815715050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
815715050
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1679778281
Short name T529
Test name
Test status
Simulation time 38836753 ps
CPU time 0.78 seconds
Started May 07 01:23:22 PM PDT 24
Finished May 07 01:23:24 PM PDT 24
Peak memory 206036 kb
Host smart-9364d8f3-3fe0-49d7-80c2-32d242ec5e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679778281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1679778281
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2488105684
Short name T172
Test name
Test status
Simulation time 616757017 ps
CPU time 15.93 seconds
Started May 07 01:23:21 PM PDT 24
Finished May 07 01:23:38 PM PDT 24
Peak memory 236412 kb
Host smart-987821e8-240e-42b1-b5f3-9c2a03e1d8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488105684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2488105684
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.119930142
Short name T87
Test name
Test status
Simulation time 1973107225 ps
CPU time 7.67 seconds
Started May 07 01:23:31 PM PDT 24
Finished May 07 01:23:40 PM PDT 24
Peak memory 224188 kb
Host smart-b766e96a-725c-4aa1-ae30-009e5267252d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119930142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.119930142
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.278582401
Short name T670
Test name
Test status
Simulation time 1810297305 ps
CPU time 13.23 seconds
Started May 07 01:23:13 PM PDT 24
Finished May 07 01:23:27 PM PDT 24
Peak memory 235956 kb
Host smart-0b111546-cf09-4bae-8afe-56336c2474f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278582401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.278582401
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.2017509503
Short name T37
Test name
Test status
Simulation time 36525611 ps
CPU time 1.06 seconds
Started May 07 01:23:20 PM PDT 24
Finished May 07 01:23:23 PM PDT 24
Peak memory 217704 kb
Host smart-a3eae9c3-7a38-4260-b999-aa4d8da747de
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017509503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.2017509503
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.377915185
Short name T262
Test name
Test status
Simulation time 10722179616 ps
CPU time 15.35 seconds
Started May 07 01:23:11 PM PDT 24
Finished May 07 01:23:27 PM PDT 24
Peak memory 223364 kb
Host smart-84f7c97e-7b96-4d78-9f41-dc32938dddd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377915185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
377915185
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.4081514226
Short name T188
Test name
Test status
Simulation time 13094308919 ps
CPU time 29.32 seconds
Started May 07 01:23:20 PM PDT 24
Finished May 07 01:23:51 PM PDT 24
Peak memory 223120 kb
Host smart-b25eecd3-4637-470b-b2ba-c764978eea60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081514226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.4081514226
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3007619691
Short name T558
Test name
Test status
Simulation time 1196280358 ps
CPU time 12.1 seconds
Started May 07 01:23:31 PM PDT 24
Finished May 07 01:23:44 PM PDT 24
Peak memory 218468 kb
Host smart-26a2da44-df40-4cb9-b6b2-3d3d11b9b024
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3007619691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3007619691
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1178068999
Short name T390
Test name
Test status
Simulation time 16189028008 ps
CPU time 43.47 seconds
Started May 07 01:23:23 PM PDT 24
Finished May 07 01:24:08 PM PDT 24
Peak memory 216088 kb
Host smart-89341c0b-4b0c-4636-8725-73776ddaee9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178068999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1178068999
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.4252831442
Short name T628
Test name
Test status
Simulation time 1433159558 ps
CPU time 6.09 seconds
Started May 07 01:23:47 PM PDT 24
Finished May 07 01:23:55 PM PDT 24
Peak memory 215956 kb
Host smart-ee770c24-7aa4-445e-bdab-3e7ce1c0cd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252831442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.4252831442
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.121339353
Short name T664
Test name
Test status
Simulation time 82897718 ps
CPU time 1.57 seconds
Started May 07 01:23:20 PM PDT 24
Finished May 07 01:23:23 PM PDT 24
Peak memory 216076 kb
Host smart-841943c5-625b-4c14-aa8c-6f5ec2c2d18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121339353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.121339353
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3833274453
Short name T528
Test name
Test status
Simulation time 52449394 ps
CPU time 0.85 seconds
Started May 07 01:23:36 PM PDT 24
Finished May 07 01:23:38 PM PDT 24
Peak memory 205432 kb
Host smart-1472cf3e-f935-4bf0-96b6-271a5640f99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833274453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3833274453
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3031899949
Short name T684
Test name
Test status
Simulation time 58460476 ps
CPU time 0.75 seconds
Started May 07 01:23:31 PM PDT 24
Finished May 07 01:23:33 PM PDT 24
Peak memory 204528 kb
Host smart-ce8673cc-28d4-40ad-b6a1-891cac00f145
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031899949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
031899949
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2198927183
Short name T683
Test name
Test status
Simulation time 16341234 ps
CPU time 0.77 seconds
Started May 07 01:23:33 PM PDT 24
Finished May 07 01:23:35 PM PDT 24
Peak memory 206420 kb
Host smart-64307929-25f1-4a6e-8b9e-1d331b13fe6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198927183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2198927183
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2226521552
Short name T358
Test name
Test status
Simulation time 744259967 ps
CPU time 11.88 seconds
Started May 07 01:23:35 PM PDT 24
Finished May 07 01:23:48 PM PDT 24
Peak memory 230620 kb
Host smart-ddb66b96-ba63-4d5f-bfcd-b117cba75d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226521552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2226521552
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.4211653955
Short name T692
Test name
Test status
Simulation time 27161724 ps
CPU time 0.98 seconds
Started May 07 01:23:28 PM PDT 24
Finished May 07 01:23:30 PM PDT 24
Peak memory 217736 kb
Host smart-592abb20-4b79-4320-a850-0d296b6ba98b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211653955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.4211653955
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2471873858
Short name T285
Test name
Test status
Simulation time 916892682 ps
CPU time 7.06 seconds
Started May 07 01:23:32 PM PDT 24
Finished May 07 01:23:41 PM PDT 24
Peak memory 216428 kb
Host smart-ae25b72d-3591-4413-85e9-9b451a34fef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471873858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2471873858
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1481725506
Short name T522
Test name
Test status
Simulation time 2497743991 ps
CPU time 9.01 seconds
Started May 07 01:23:34 PM PDT 24
Finished May 07 01:23:44 PM PDT 24
Peak memory 218960 kb
Host smart-64511d8e-ddbf-4985-b0d5-9d4b763fe16d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1481725506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1481725506
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1390367450
Short name T396
Test name
Test status
Simulation time 697983508 ps
CPU time 2.97 seconds
Started May 07 01:23:38 PM PDT 24
Finished May 07 01:23:42 PM PDT 24
Peak memory 217180 kb
Host smart-07b560c4-d1cc-4c5d-a886-bf35dde803bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390367450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1390367450
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2161796621
Short name T479
Test name
Test status
Simulation time 3092762406 ps
CPU time 9.14 seconds
Started May 07 01:23:24 PM PDT 24
Finished May 07 01:23:34 PM PDT 24
Peak memory 216060 kb
Host smart-0eeb27d4-a53b-4005-b951-456fe7a51892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161796621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2161796621
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.859047146
Short name T482
Test name
Test status
Simulation time 134565898 ps
CPU time 1.38 seconds
Started May 07 01:23:26 PM PDT 24
Finished May 07 01:23:28 PM PDT 24
Peak memory 215960 kb
Host smart-443f03d5-53d2-41ac-9f94-5608862a6979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859047146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.859047146
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2027778931
Short name T686
Test name
Test status
Simulation time 50553354 ps
CPU time 0.72 seconds
Started May 07 01:23:36 PM PDT 24
Finished May 07 01:23:37 PM PDT 24
Peak memory 205432 kb
Host smart-9c54913c-b61a-4c6a-b56c-634599f8e2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027778931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2027778931
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.283444347
Short name T544
Test name
Test status
Simulation time 23963664 ps
CPU time 0.67 seconds
Started May 07 01:23:49 PM PDT 24
Finished May 07 01:23:52 PM PDT 24
Peak memory 204988 kb
Host smart-a345ddbe-a6b1-4e20-b300-566f32b3ae0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283444347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.283444347
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2522153755
Short name T454
Test name
Test status
Simulation time 62368177 ps
CPU time 0.78 seconds
Started May 07 01:23:37 PM PDT 24
Finished May 07 01:23:40 PM PDT 24
Peak memory 206112 kb
Host smart-a30630ec-a332-417f-80c9-2be8cdec6fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522153755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2522153755
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_intercept.849415416
Short name T219
Test name
Test status
Simulation time 238539937 ps
CPU time 5.14 seconds
Started May 07 01:23:41 PM PDT 24
Finished May 07 01:23:48 PM PDT 24
Peak memory 216320 kb
Host smart-d9295bbf-db37-4322-80f1-b774d3881f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849415416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.849415416
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2026485131
Short name T174
Test name
Test status
Simulation time 8656155115 ps
CPU time 26.76 seconds
Started May 07 01:23:39 PM PDT 24
Finished May 07 01:24:06 PM PDT 24
Peak memory 234992 kb
Host smart-3fab92d9-2540-4e62-aada-7c7d82cc96ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026485131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2026485131
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.944743531
Short name T690
Test name
Test status
Simulation time 61535694 ps
CPU time 1 seconds
Started May 07 01:23:50 PM PDT 24
Finished May 07 01:23:54 PM PDT 24
Peak memory 216488 kb
Host smart-30bc2477-49dd-495b-ac09-e882598a3057
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944743531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.spi_device_mem_parity.944743531
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1096985586
Short name T554
Test name
Test status
Simulation time 763366025 ps
CPU time 4.45 seconds
Started May 07 01:23:40 PM PDT 24
Finished May 07 01:23:46 PM PDT 24
Peak memory 222212 kb
Host smart-e26b4a22-a574-4313-91e6-ba01b06f9bfa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1096985586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1096985586
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.648273092
Short name T386
Test name
Test status
Simulation time 1667154224 ps
CPU time 20.32 seconds
Started May 07 01:23:36 PM PDT 24
Finished May 07 01:23:58 PM PDT 24
Peak memory 216116 kb
Host smart-6b8fec9e-9cc4-4f1e-ab3e-7f1b67a090df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648273092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.648273092
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.4292823002
Short name T459
Test name
Test status
Simulation time 12664184376 ps
CPU time 18.68 seconds
Started May 07 01:23:23 PM PDT 24
Finished May 07 01:23:43 PM PDT 24
Peak memory 216072 kb
Host smart-40073d31-eaff-40c8-b04b-a9b647ff7ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292823002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.4292823002
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2792973607
Short name T727
Test name
Test status
Simulation time 17444511 ps
CPU time 1.1 seconds
Started May 07 01:23:33 PM PDT 24
Finished May 07 01:23:36 PM PDT 24
Peak memory 207860 kb
Host smart-d4eee636-1ad7-4e86-b73b-35bd64e7da8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792973607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2792973607
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3707652004
Short name T599
Test name
Test status
Simulation time 194039517 ps
CPU time 0.78 seconds
Started May 07 01:23:35 PM PDT 24
Finished May 07 01:23:37 PM PDT 24
Peak memory 205444 kb
Host smart-a433bfdc-9643-43c8-bbd2-9c5b1fd792e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707652004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3707652004
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1516766864
Short name T735
Test name
Test status
Simulation time 2029780947 ps
CPU time 7.16 seconds
Started May 07 01:23:36 PM PDT 24
Finished May 07 01:23:45 PM PDT 24
Peak memory 236792 kb
Host smart-497a4c06-1003-4f1d-ae5c-cdb340b1c8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516766864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1516766864
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1499738859
Short name T460
Test name
Test status
Simulation time 113732545 ps
CPU time 0.7 seconds
Started May 07 01:23:36 PM PDT 24
Finished May 07 01:23:38 PM PDT 24
Peak memory 205084 kb
Host smart-bb0f7a79-43fc-4663-b28f-cb88d025b867
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499738859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
499738859
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1417728176
Short name T489
Test name
Test status
Simulation time 78842405 ps
CPU time 2.54 seconds
Started May 07 01:23:36 PM PDT 24
Finished May 07 01:23:39 PM PDT 24
Peak memory 222708 kb
Host smart-02a19f79-27b6-4316-af85-f78b9415e5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417728176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1417728176
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.260564425
Short name T623
Test name
Test status
Simulation time 71812530 ps
CPU time 0.8 seconds
Started May 07 01:23:33 PM PDT 24
Finished May 07 01:23:36 PM PDT 24
Peak memory 206092 kb
Host smart-67ac70fb-c768-4370-9390-3a8d22d22a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260564425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.260564425
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3535377507
Short name T368
Test name
Test status
Simulation time 3672979946 ps
CPU time 27.5 seconds
Started May 07 01:23:53 PM PDT 24
Finished May 07 01:24:23 PM PDT 24
Peak memory 250068 kb
Host smart-4715dbdf-72c8-4c72-9b2e-16160412860e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535377507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3535377507
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2484542249
Short name T243
Test name
Test status
Simulation time 3352303143 ps
CPU time 8.78 seconds
Started May 07 01:23:30 PM PDT 24
Finished May 07 01:23:41 PM PDT 24
Peak memory 217228 kb
Host smart-9c989e88-fc8a-4168-87dd-459f7418fb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484542249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2484542249
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.3801727350
Short name T716
Test name
Test status
Simulation time 49576053 ps
CPU time 1.04 seconds
Started May 07 01:23:40 PM PDT 24
Finished May 07 01:23:42 PM PDT 24
Peak memory 216492 kb
Host smart-950d9f72-e83e-4ce9-b11f-cf2c44e30342
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801727350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.3801727350
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.83401095
Short name T244
Test name
Test status
Simulation time 5408064630 ps
CPU time 18.61 seconds
Started May 07 01:23:44 PM PDT 24
Finished May 07 01:24:04 PM PDT 24
Peak memory 235848 kb
Host smart-7292eccf-bed0-4378-8409-b42b4bc574f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83401095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.83401095
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3788414591
Short name T4
Test name
Test status
Simulation time 876280690 ps
CPU time 11.73 seconds
Started May 07 01:23:34 PM PDT 24
Finished May 07 01:23:47 PM PDT 24
Peak memory 219800 kb
Host smart-bbe8dec0-1d3e-4f43-8217-4586b7e8fd68
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3788414591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3788414591
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.4288768943
Short name T105
Test name
Test status
Simulation time 1717811295 ps
CPU time 5.88 seconds
Started May 07 01:23:45 PM PDT 24
Finished May 07 01:23:52 PM PDT 24
Peak memory 216076 kb
Host smart-f7d2c636-9b2f-454d-87d0-11b41b28d60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288768943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.4288768943
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3460572399
Short name T589
Test name
Test status
Simulation time 66942859 ps
CPU time 1.17 seconds
Started May 07 01:23:37 PM PDT 24
Finished May 07 01:23:40 PM PDT 24
Peak memory 215836 kb
Host smart-83d074d5-042b-4e6a-bc10-832b411ed68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460572399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3460572399
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2941118559
Short name T477
Test name
Test status
Simulation time 196156887 ps
CPU time 0.86 seconds
Started May 07 01:23:37 PM PDT 24
Finished May 07 01:23:39 PM PDT 24
Peak memory 205440 kb
Host smart-9ec2b62f-aa73-40dc-8b21-7111a901c439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941118559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2941118559
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2810716833
Short name T313
Test name
Test status
Simulation time 129626198 ps
CPU time 2.48 seconds
Started May 07 01:23:23 PM PDT 24
Finished May 07 01:23:27 PM PDT 24
Peak memory 221436 kb
Host smart-b46d1b70-eb54-4a0e-a96d-c78523bbc7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810716833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2810716833
Directory /workspace/9.spi_device_upload/latest
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