Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2445005	1			T1	1		T2	39106		T3	62
all_values[1]	2445005	1			T1	1		T2	39106		T3	62
all_values[2]	2445005	1			T1	1		T2	39106		T3	62
all_values[3]	2445005	1			T1	1		T2	39106		T3	62
all_values[4]	2445005	1			T1	1		T2	39106		T3	62
all_values[5]	2445005	1			T1	1		T2	39106		T3	62
all_values[6]	2445005	1			T1	1		T2	39106		T3	62
all_values[7]	2445005	1			T1	1		T2	39106		T3	62

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18866125

1

T1

8

T2

312848

T3

496

auto[1]

693915

1

T19

35

T59

25

T61

14244

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19539567

1

T1

8

T2

312801

T3

490

auto[1]

20473

1

T2

47

T3

6

T10

2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2361849	1			T1	1		T2	39069		T3	62
all_values[0]	auto[0]	auto[1]	10802	1			T2	37		T10	2		T13	34
all_values[0]	auto[1]	auto[0]	72094	1			T19	2		T59	1		T60	6
all_values[0]	auto[1]	auto[1]	260	1			T19	6		T60	2		T62	3
all_values[1]	auto[0]	auto[0]	2328053	1			T1	1		T2	39096		T3	62
all_values[1]	auto[0]	auto[1]	4911	1			T2	10		T13	28		T19	13
all_values[1]	auto[1]	auto[0]	111552	1			T19	3		T59	6		T61	1
all_values[1]	auto[1]	auto[1]	489	1			T19	1		T61	1		T60	5
all_values[2]	auto[0]	auto[0]	2410118	1			T1	1		T2	39106		T3	62
all_values[2]	auto[0]	auto[1]	1856	1			T19	4		T41	71		T59	3
all_values[2]	auto[1]	auto[0]	32745	1			T19	1		T61	2811		T60	1
all_values[2]	auto[1]	auto[1]	286	1			T19	2		T59	1		T61	37
all_values[3]	auto[0]	auto[0]	2332086	1			T1	1		T2	39106		T3	62
all_values[3]	auto[0]	auto[1]	167	1			T19	2		T59	1		T61	1
all_values[3]	auto[1]	auto[0]	112578	1			T19	4		T59	5		T61	2846
all_values[3]	auto[1]	auto[1]	174	1			T61	1		T60	3		T62	6
all_values[4]	auto[0]	auto[0]	2402771	1			T1	1		T2	39106		T3	62
all_values[4]	auto[0]	auto[1]	184	1			T11	3		T37	3		T19	3
all_values[4]	auto[1]	auto[0]	41864	1			T19	3		T59	1		T61	1
all_values[4]	auto[1]	auto[1]	186	1			T19	2		T61	2		T62	3
all_values[5]	auto[0]	auto[0]	2331875	1			T1	1		T2	39106		T3	56
all_values[5]	auto[0]	auto[1]	313	1			T3	6		T19	1		T59	1
all_values[5]	auto[1]	auto[0]	112657	1			T19	1		T59	4		T61	2845
all_values[5]	auto[1]	auto[1]	160	1			T19	2		T59	1		T61	3
all_values[6]	auto[0]	auto[0]	2329976	1			T1	1		T2	39106		T3	62
all_values[6]	auto[0]	auto[1]	161	1			T19	1		T59	3		T61	2
all_values[6]	auto[1]	auto[0]	114689	1			T19	3		T59	1		T61	2847
all_values[6]	auto[1]	auto[1]	179	1			T19	3		T61	1		T60	1
all_values[7]	auto[0]	auto[0]	2350836	1			T1	1		T2	39106		T3	62
all_values[7]	auto[0]	auto[1]	167	1			T19	3		T61	1		T60	1
all_values[7]	auto[1]	auto[0]	93824	1			T19	1		T59	3		T61	2845
all_values[7]	auto[1]	auto[1]	178	1			T19	1		T59	2		T61	3