Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	29057	1			T2	44		T4	6		T6	4
auto[SpiFlashAddrCfg]	6101	1			T2	21		T4	4		T6	10
auto[SpiFlashAddr3b]	7550	1			T2	29		T6	2		T7	36
auto[SpiFlashAddr4b]	6080	1			T2	16		T4	4		T6	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27945

1

T2

75

T4

14

T6

18

auto[1]

20843

1

T2

35

T7

334

T10

172

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25883

1

T2

52

T4

12

T6

6

auto[1]

22905

1

T2

58

T4

2

T6

12

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	32849	1			T2	55		T4	6		T6	6
values[1]	902	1			T2	1		T6	2		T7	7
values[2]	1225	1			T2	1		T4	2		T7	7
values[3]	1098	1			T2	6		T7	5		T10	5
values[4]	1115	1			T2	3		T7	6		T10	12
values[5]	1199	1			T2	5		T7	6		T10	13
values[6]	1216	1			T2	9		T7	2		T8	4
values[7]	1171	1			T2	5		T4	2		T7	9
values[8]	8013	1			T2	25		T4	4		T6	10

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26212

1

T2

110

T4

14

T6

18

auto[1]

22576

1

T7

533

T11

4

T36

56

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

46957

1

T2

107

T4

14

T6

18

write

1831

1

T2

3

T7

12

T8

4

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

15980

1

T2

53

T4

8

T6

6

valids[0x1]

32808

1

T2

57

T4

6

T6

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1226	1			T2	1		T6	2		T7	3
internal_process_ops[0x5a]	1233	1			T2	2		T7	4		T8	2
internal_process_ops[0x05]	17962	1			T2	13		T6	2		T7	321
internal_process_ops[0x35]	1205	1			T2	2		T7	10		T8	2
internal_process_ops[0x15]	1322	1			T2	7		T4	2		T7	7
internal_process_ops[0x03]	898	1			T2	2		T7	1		T10	10
internal_process_ops[0x0b]	899	1			T2	4		T7	4		T10	7
internal_process_ops[0x3b]	950	1			T2	7		T7	7		T10	7
internal_process_ops[0x6b]	893	1			T2	4		T4	2		T7	3
internal_process_ops[0xbb]	844	1			T2	5		T7	1		T10	4
internal_process_ops[0xeb]	932	1			T2	4		T7	2		T10	7

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47913

1

T2

110

T4

14

T6

18

auto[1]

875

1

T7

4

T10

8

T13

7

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47031

1

T2

106

T4

14

T6

18

auto[1]

1757

1

T2

4

T7

20

T10

14

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8708

1

T2

38

T4

6

T6

4

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5603

1

T2

6

T10

97

T13

30

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1873

1

T2

4

T4

4

T6

10

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1563

1

T2

17

T10

21

T13

27

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2295

1

T2

18

T6

2

T8

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1912

1

T2

9

T10

25

T13

22

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1716

1

T2

14

T4

4

T6

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1595

1

T2

1

T10

26

T13

30

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

56

1

T13

1

T28

2

T32

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

56

1

T10

2

T28

2

T32

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

55

1

T28

1

T19

1

T30

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

50

1

T13

1

T28

1

T19

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

64

1

T8

4

T10

5

T30

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

81

1

T10

4

T13

4

T59

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

42

1

T13

2

T28

2

T19

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

59

1

T13

2

T55

1

T29

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

61

1

T169

2

T28

3

T19

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

47

1

T28

1

T19

3

T29

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

67

1

T2

2

T10

1

T28

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

53

1

T30

2

T32

1

T170

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

90

1

T2

1

T35

4

T13

5

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

46

1

T29

2

T30

1

T32

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

57

1

T13

1

T19

1

T55

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

63

1

T10

2

T19

1

T31

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8662

1

T7

137

T36

27

T27

142

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5650

1

T7

264

T36

6

T27

131

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1065

1

T7

22

T36

1

T27

9

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1139

1

T7

24

T36

8

T27

8

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1492

1

T7

12

T37

2

T27

23

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1411

1

T7

20

T36

5

T27

12

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1177

1

T7

24

T11

4

T36

6

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1096

1

T7

18

T36

1

T27

19

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

59

1

T40

1

T42

1

T171

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

48

1

T27

1

T20

2

T42

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

68

1

T171

2

T21

2

T172

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

42

1

T7

2

T36

2

T27

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

63

1

T40

3

T20

1

T61

5

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

60

1

T42

1

T58

1

T171

5

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

38

1

T40

2

T41

1

T42

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

54

1

T40

2

T20

1

T42

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

52

1

T7

2

T40

1

T20

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

57

1

T40

3

T41

2

T58

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

49

1

T7

2

T27

1

T173

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

54

1

T27

1

T173

1

T58

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

64

1

T7

1

T27

1

T61

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

53

1

T7

1

T27

2

T20

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

71

1

T7

3

T42

2

T58

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

52

1

T7

1

T20

1

T41

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3487	1			T2	19		T4	4		T8	2
auto[0]	values[0]	valids[0x1]	13152	1			T2	36		T4	2		T6	6
auto[0]	values[1]	valids[0x1]	507	1			T2	1		T6	2		T10	7
auto[0]	values[2]	valids[0x0]	454	1			T2	1		T10	5		T13	1
auto[0]	values[2]	valids[0x1]	238	1			T4	2		T10	3		T13	4
auto[0]	values[3]	valids[0x0]	475	1			T2	3		T10	2		T13	5
auto[0]	values[3]	valids[0x1]	225	1			T2	3		T10	3		T13	2
auto[0]	values[4]	valids[0x0]	418	1			T2	3		T10	10		T13	3
auto[0]	values[4]	valids[0x1]	238	1			T10	2		T35	2		T13	5
auto[0]	values[5]	valids[0x0]	485	1			T2	4		T10	6		T13	10
auto[0]	values[5]	valids[0x1]	232	1			T2	1		T10	7		T13	7
auto[0]	values[6]	valids[0x0]	492	1			T2	4		T10	4		T13	7
auto[0]	values[6]	valids[0x1]	286	1			T2	5		T8	4		T10	2
auto[0]	values[7]	valids[0x0]	450	1			T2	3		T10	8		T13	10
auto[0]	values[7]	valids[0x1]	235	1			T2	2		T4	2		T10	5
auto[0]	values[8]	valids[0x0]	3022	1			T2	16		T4	4		T6	6
auto[0]	values[8]	valids[0x1]	1816	1			T2	9		T6	4		T10	21
auto[1]	values[0]	valids[0x0]	3166	1			T7	62		T36	7		T27	41
auto[1]	values[0]	valids[0x1]	13044	1			T7	374		T36	34		T27	241
auto[1]	values[1]	valids[0x1]	395	1			T7	7		T27	7		T40	5
auto[1]	values[2]	valids[0x0]	313	1			T7	4		T36	2		T27	2
auto[1]	values[2]	valids[0x1]	220	1			T7	3		T27	2		T40	5
auto[1]	values[3]	valids[0x0]	232	1			T7	4		T27	1		T40	7
auto[1]	values[3]	valids[0x1]	166	1			T7	1		T40	1		T20	3
auto[1]	values[4]	valids[0x0]	293	1			T7	4		T11	2		T36	1
auto[1]	values[4]	valids[0x1]	166	1			T7	2		T36	3		T27	2
auto[1]	values[5]	valids[0x0]	297	1			T7	1		T27	1		T40	4
auto[1]	values[5]	valids[0x1]	185	1			T7	5		T36	2		T27	1
auto[1]	values[6]	valids[0x0]	259	1			T7	2		T27	3		T40	5
auto[1]	values[6]	valids[0x1]	179	1			T27	1		T20	2		T42	1
auto[1]	values[7]	valids[0x0]	298	1			T7	6		T40	3		T20	2
auto[1]	values[7]	valids[0x1]	188	1			T7	3		T11	2		T27	9
auto[1]	values[8]	valids[0x0]	1839	1			T7	32		T36	2		T27	21
auto[1]	values[8]	valids[0x1]	1336	1			T7	23		T36	5		T37	2