Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3162536

1

T1

1

T2

12515

T4

5739

auto[1]

16700

1

T2

10

T7

313

T10

274

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1107533

1

T1

1

T2

26

T4

1

auto[1]

2071703

1

T2

12499

T4

5738

T6

3602

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	589584	1			T1	1		T2	1095		T4	5739
auto[524288:1048575]	340754	1			T2	6		T7	909		T10	3
auto[1048576:1572863]	427126	1			T2	512		T7	20		T10	16
auto[1572864:2097151]	394003	1			T2	7		T7	623		T10	1071
auto[2097152:2621439]	333823	1			T2	3692		T7	2795		T10	3602
auto[2621440:3145727]	341632	1			T2	5		T7	2397		T10	3962
auto[3145728:3670015]	377614	1			T2	2679		T7	2454		T10	594
auto[3670016:4194303]	374700	1			T2	4529		T7	389		T10	6257

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2092238

1

T1

1

T2

12523

T4

5739

auto[1]

1086998

1

T2

2

T7

17

T10

6

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2777322

1

T1

1

T2

6810

T4

5739

auto[1]

401914

1

T2

5715

T7

3093

T10

560

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	212910	1			T1	1		T4	1		T6	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	300680	1			T2	1095		T4	5738		T6	3602
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	103035	1			T2	2		T7	4		T10	3
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	183660	1			T2	1		T7	774		T13	514
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	141515	1			T7	2		T10	2		T35	26
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	224260	1			T2	512		T7	1		T10	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	140316	1			T2	1		T7	8		T10	3
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	191312	1			T2	1		T7	546		T10	1057
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	110269	1			T2	2		T7	8		T10	9
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	192116	1			T2	129		T7	2736		T10	3558
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	130558	1			T2	3		T7	4		T10	8
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	173394	1			T2	1		T7	9		T10	3623
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	136835	1			T2	2		T7	7		T10	7
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	187434	1			T2	522		T7	2406		T10	258
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	120497	1			T2	6		T7	11		T10	3
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	215025	1			T2	4523		T7	241		T10	6254
auto[0]	auto[1]	auto[0:524287]	auto[0]	1360	1			T7	1		T10	3		T115	61
auto[0]	auto[1]	auto[0:524287]	auto[1]	71946	1			T7	512		T27	8		T28	2916
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	2490	1			T7	1		T115	7		T27	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	49411	1			T7	128		T27	808		T28	512
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	574	1			T36	1		T27	1		T28	4
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	58568	1			T36	1070		T28	640		T20	265
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1618	1			T10	1		T13	6		T36	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	59024	1			T13	771		T36	1		T20	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	276	1			T2	5		T10	1		T13	4
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	29182	1			T2	3555		T10	1		T13	5
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	933	1			T10	7		T36	1		T115	3
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	35312	1			T7	2377		T10	258		T28	128
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	445	1			T2	1		T10	3		T115	7
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	50754	1			T2	2154		T7	2		T10	256
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	2142	1			T7	6		T115	6		T28	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	34685	1			T7	3		T32	385		T42	1
auto[1]	auto[0]	auto[0:524287]	auto[0]	247	1			T10	2		T13	2		T27	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	2111	1			T10	80		T13	2		T27	11
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	193	1			T2	1		T7	1		T13	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1604	1			T2	2		T7	1		T13	39
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	184	1			T7	1		T10	1		T13	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1569	1			T7	16		T10	12		T13	46
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	139	1			T2	1		T7	3		T10	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1115	1			T2	4		T7	66		T10	9
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	185	1			T2	1		T7	5		T10	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1535	1			T7	46		T10	22		T13	65
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	133	1			T2	1		T7	1		T10	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	884	1			T7	6		T10	42		T27	34
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	177	1			T7	3		T10	2		T28	3
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1627	1			T7	36		T10	68		T28	33
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	175	1			T7	3		T13	1		T28	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1628	1			T7	62		T13	9		T28	11
auto[1]	auto[1]	auto[0:524287]	auto[0]	38	1			T27	1		T28	1		T55	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	292	1			T28	17		T55	28		T31	20
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	35	1			T27	1		T192	4		T294	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	326	1			T27	49		T192	10		T295	51
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	50	1			T20	2		T30	1		T31	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	406	1			T20	19		T30	17		T31	25
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	46	1			T13	3		T36	1		T20	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	433	1			T13	77		T36	15		T20	54
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	27	1			T10	1		T13	1		T28	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	233	1			T10	7		T13	20		T28	11
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	53	1			T10	2		T40	1		T41	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	365	1			T10	20		T40	6		T41	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	27	1			T58	1		T33	1		T78	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	315	1			T58	3		T33	5		T78	11
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	51	1			T7	3		T32	1		T42	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	497	1			T7	60		T32	1		T42	33

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1684741	1			T1	1		T2	6800		T4	5739
auto[0]	auto[0]	auto[1]	1079075	1			T7	8		T10	6		T11	987
auto[0]	auto[1]	auto[0]	391188	1			T2	5715		T7	3027		T10	530
auto[0]	auto[1]	auto[1]	7532	1			T7	3		T13	3		T115	2
auto[1]	auto[0]	auto[0]	13191	1			T2	8		T7	245		T10	244
auto[1]	auto[0]	auto[1]	315	1			T2	2		T7	5		T13	1
auto[1]	auto[1]	auto[0]	3118	1			T7	62		T10	30		T13	100
auto[1]	auto[1]	auto[1]	76	1			T7	1		T13	1		T40	1