Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15093

1

T2

75

T4

14

T6

18

auto[1]

11119

1

T2

35

T10

172

T13

115

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3325	1			T10	20		T35	8		T13	40
values[1]	3270	1			T8	20		T10	20		T13	63
values[2]	3450	1			T4	14		T10	150		T39	12
values[3]	3327	1			T10	113		T13	43		T182	6
values[4]	2846	1			T2	20		T10	20		T28	152
values[5]	3363	1			T2	28		T6	18		T10	20
values[6]	3153	1			T2	22		T10	151		T13	126
values[7]	3478	1			T2	40		T13	207		T169	4

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3516	1			T2	20		T4	14		T10	113
values[1]	3079	1			T10	41		T13	23		T197	14
values[2]	2975	1			T8	20		T10	20		T13	227
values[3]	2868	1			T10	144		T13	20		T28	78
values[4]	3808	1			T2	22		T10	66		T35	8
values[5]	3122	1			T2	20		T10	20		T13	20
values[6]	3503	1			T2	48		T6	18		T13	106
values[7]	3341	1			T10	90		T13	31		T182	6

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	296	1			T28	9		T198	10		T180	14
auto[0]	values[0]	values[1]	200	1			T29	12		T163	16		T86	10
auto[0]	values[0]	values[2]	133	1			T62	11		T185	10		T175	10
auto[0]	values[0]	values[3]	273	1			T59	8		T296	2		T234	29
auto[0]	values[0]	values[4]	266	1			T10	10		T35	8		T13	14
auto[0]	values[0]	values[5]	275	1			T13	11		T28	13		T31	14
auto[0]	values[0]	values[6]	254	1			T31	9		T32	13		T33	12
auto[0]	values[0]	values[7]	173	1			T215	6		T185	10		T297	8
auto[0]	values[1]	values[0]	239	1			T13	8		T55	10		T59	14
auto[0]	values[1]	values[1]	320	1			T13	15		T28	71		T201	6
auto[0]	values[1]	values[2]	262	1			T8	20		T178	2		T246	7
auto[0]	values[1]	values[3]	179	1			T10	15		T13	13		T194	10
auto[0]	values[1]	values[4]	214	1			T192	13		T298	8		T227	10
auto[0]	values[1]	values[5]	272	1			T55	11		T62	9		T175	18
auto[0]	values[1]	values[6]	223	1			T55	99		T185	34		T209	2
auto[0]	values[1]	values[7]	233	1			T33	14		T174	14		T23	27
auto[0]	values[2]	values[0]	236	1			T4	14		T32	8		T62	9
auto[0]	values[2]	values[1]	322	1			T32	14		T62	14		T281	14
auto[0]	values[2]	values[2]	154	1			T32	16		T62	25		T72	4
auto[0]	values[2]	values[3]	135	1			T10	15		T206	18		T34	11
auto[0]	values[2]	values[4]	184	1			T10	20		T19	14		T30	13
auto[0]	values[2]	values[5]	277	1			T10	9		T39	12		T32	13
auto[0]	values[2]	values[6]	279	1			T28	13		T59	15		T62	16
auto[0]	values[2]	values[7]	263	1			T189	10		T192	14		T202	15
auto[0]	values[3]	values[0]	445	1			T10	101		T13	33		T19	34
auto[0]	values[3]	values[1]	205	1			T28	13		T59	10		T208	2
auto[0]	values[3]	values[2]	175	1			T33	47		T185	16		T177	24
auto[0]	values[3]	values[3]	161	1			T175	15		T192	11		T177	12
auto[0]	values[3]	values[4]	129	1			T292	18		T34	9		T283	10
auto[0]	values[3]	values[5]	297	1			T175	7		T192	9		T170	92
auto[0]	values[3]	values[6]	276	1			T183	12		T185	13		T188	14
auto[0]	values[3]	values[7]	418	1			T182	6		T28	13		T32	14
auto[0]	values[4]	values[0]	127	1			T30	11		T191	16		T202	10
auto[0]	values[4]	values[1]	124	1			T62	12		T188	9		T43	11
auto[0]	values[4]	values[2]	198	1			T10	12		T28	11		T31	12
auto[0]	values[4]	values[3]	232	1			T28	64		T19	9		T179	22
auto[0]	values[4]	values[4]	248	1			T211	2		T184	12		T43	9
auto[0]	values[4]	values[5]	248	1			T2	14		T62	15		T183	97
auto[0]	values[4]	values[6]	244	1			T31	13		T59	25		T33	19
auto[0]	values[4]	values[7]	117	1			T30	13		T205	4		T180	11
auto[0]	values[5]	values[0]	332	1			T200	14		T189	13		T185	15
auto[0]	values[5]	values[1]	111	1			T197	14		T299	2		T185	19
auto[0]	values[5]	values[2]	172	1			T32	10		T189	10		T270	10
auto[0]	values[5]	values[3]	189	1			T10	11		T31	15		T189	16
auto[0]	values[5]	values[4]	296	1			T28	20		T30	15		T31	19
auto[0]	values[5]	values[5]	201	1			T115	24		T30	27		T32	9
auto[0]	values[5]	values[6]	346	1			T2	26		T6	18		T30	45
auto[0]	values[5]	values[7]	358	1			T13	22		T300	10		T301	16
auto[0]	values[6]	values[0]	107	1			T19	9		T302	4		T207	10
auto[0]	values[6]	values[1]	226	1			T10	31		T19	8		T31	21
auto[0]	values[6]	values[2]	263	1			T13	9		T28	11		T192	7
auto[0]	values[6]	values[3]	275	1			T19	22		T30	10		T185	13
auto[0]	values[6]	values[4]	341	1			T2	14		T10	16		T32	15
auto[0]	values[6]	values[5]	162	1			T31	24		T175	17		T303	10
auto[0]	values[6]	values[6]	235	1			T13	74		T30	40		T62	46
auto[0]	values[6]	values[7]	234	1			T10	82		T19	8		T162	2
auto[0]	values[7]	values[0]	246	1			T2	12		T29	29		T30	18
auto[0]	values[7]	values[1]	179	1			T216	6		T180	10		T23	15
auto[0]	values[7]	values[2]	358	1			T13	196		T92	12		T33	5
auto[0]	values[7]	values[3]	134	1			T189	10		T170	73		T204	17
auto[0]	values[7]	values[4]	224	1			T28	24		T193	16		T240	11
auto[0]	values[7]	values[5]	236	1			T33	14		T210	24		T234	15
auto[0]	values[7]	values[6]	304	1			T2	9		T169	4		T33	28
auto[0]	values[7]	values[7]	258	1			T28	26		T29	28		T30	10
auto[1]	values[0]	values[0]	174	1			T28	11		T198	10		T180	6
auto[1]	values[0]	values[1]	82	1			T29	8		T189	9		T23	8
auto[1]	values[0]	values[2]	203	1			T62	18		T185	11		T175	11
auto[1]	values[0]	values[3]	127	1			T59	12		T234	10		T175	9
auto[1]	values[0]	values[4]	157	1			T10	10		T13	6		T79	28
auto[1]	values[0]	values[5]	276	1			T13	9		T28	7		T31	72
auto[1]	values[0]	values[6]	329	1			T31	37		T32	7		T33	14
auto[1]	values[0]	values[7]	107	1			T185	11		T240	10		T204	10
auto[1]	values[1]	values[0]	227	1			T13	12		T55	10		T59	6
auto[1]	values[1]	values[1]	183	1			T13	8		T28	7		T191	5
auto[1]	values[1]	values[2]	216	1			T246	66		T192	5		T177	6
auto[1]	values[1]	values[3]	183	1			T10	5		T13	7		T188	8
auto[1]	values[1]	values[4]	154	1			T192	7		T227	10		T160	10
auto[1]	values[1]	values[5]	128	1			T55	9		T62	20		T175	9
auto[1]	values[1]	values[6]	99	1			T55	11		T185	7		T227	13
auto[1]	values[1]	values[7]	138	1			T33	27		T23	18		T47	15
auto[1]	values[2]	values[0]	248	1			T32	19		T62	11		T191	8
auto[1]	values[2]	values[1]	309	1			T32	7		T62	13		T177	11
auto[1]	values[2]	values[2]	82	1			T32	5		T62	7		T240	10
auto[1]	values[2]	values[3]	273	1			T10	89		T34	18		T23	31
auto[1]	values[2]	values[4]	234	1			T10	6		T19	126		T30	7
auto[1]	values[2]	values[5]	116	1			T10	11		T32	12		T59	12
auto[1]	values[2]	values[6]	116	1			T28	7		T59	5		T62	8
auto[1]	values[2]	values[7]	222	1			T189	10		T192	14		T202	9
auto[1]	values[3]	values[0]	147	1			T10	12		T13	10		T19	11
auto[1]	values[3]	values[1]	203	1			T28	21		T59	14		T23	7
auto[1]	values[3]	values[2]	133	1			T33	8		T269	18		T185	4
auto[1]	values[3]	values[3]	91	1			T175	10		T192	19		T177	8
auto[1]	values[3]	values[4]	70	1			T34	15		T283	10		T140	8
auto[1]	values[3]	values[5]	145	1			T175	14		T192	11		T170	6
auto[1]	values[3]	values[6]	94	1			T183	8		T185	38		T188	11
auto[1]	values[3]	values[7]	338	1			T28	85		T32	12		T62	11
auto[1]	values[4]	values[0]	155	1			T30	31		T304	4		T282	20
auto[1]	values[4]	values[1]	191	1			T62	8		T69	18		T188	11
auto[1]	values[4]	values[2]	160	1			T10	8		T28	63		T31	8
auto[1]	values[4]	values[3]	188	1			T28	14		T19	11		T227	28
auto[1]	values[4]	values[4]	221	1			T248	14		T184	8		T43	11
auto[1]	values[4]	values[5]	122	1			T2	6		T62	5		T183	8
auto[1]	values[4]	values[6]	196	1			T31	7		T59	17		T33	6
auto[1]	values[4]	values[7]	75	1			T30	7		T180	9		T227	9
auto[1]	values[5]	values[0]	115	1			T189	7		T185	5		T170	12
auto[1]	values[5]	values[1]	111	1			T185	23		T175	5		T188	34
auto[1]	values[5]	values[2]	152	1			T32	10		T189	10		T23	10
auto[1]	values[5]	values[3]	181	1			T10	9		T31	5		T186	14
auto[1]	values[5]	values[4]	333	1			T28	9		T30	5		T31	107
auto[1]	values[5]	values[5]	163	1			T30	8		T32	11		T192	5
auto[1]	values[5]	values[6]	162	1			T2	2		T30	19		T32	6
auto[1]	values[5]	values[7]	141	1			T13	9		T70	12		T213	6
auto[1]	values[6]	values[0]	182	1			T19	11		T191	12		T130	7
auto[1]	values[6]	values[1]	201	1			T10	10		T19	12		T31	8
auto[1]	values[6]	values[2]	171	1			T13	11		T28	12		T192	14
auto[1]	values[6]	values[3]	181	1			T19	21		T30	10		T185	8
auto[1]	values[6]	values[4]	343	1			T2	8		T10	4		T32	5
auto[1]	values[6]	values[5]	49	1			T31	7		T175	7		T204	7
auto[1]	values[6]	values[6]	119	1			T13	32		T30	6		T62	23
auto[1]	values[6]	values[7]	64	1			T10	8		T19	12		T183	15
auto[1]	values[7]	values[0]	240	1			T2	8		T29	7		T30	36
auto[1]	values[7]	values[1]	112	1			T180	10		T23	6		T233	12
auto[1]	values[7]	values[2]	143	1			T13	11		T33	15		T175	12
auto[1]	values[7]	values[3]	66	1			T189	10		T170	11		T204	3
auto[1]	values[7]	values[4]	394	1			T28	16		T240	9		T204	9
auto[1]	values[7]	values[5]	155	1			T33	6		T234	5		T180	9
auto[1]	values[7]	values[6]	227	1			T2	11		T33	21		T195	5
auto[1]	values[7]	values[7]	202	1			T28	7		T29	7		T30	40