Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	376	1			T2	2		T10	1		T35	2
auto[ReadAddrCrossIntoMailbox]	292	1			T2	3		T10	4		T13	1
auto[ReadAddrCrossOutOfMailbox]	295	1			T2	4		T10	4		T13	2
auto[ReadAddrCrossAllMailbox]	176	1			T2	2		T10	1		T13	1
auto[ReadAddrOutsideMailbox]	3037	1			T2	15		T4	2		T8	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2072

1

T2

9

T4

1

T8

1

auto[1]

2104

1

T2

17

T4

1

T8

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	698	1			T2	2		T10	10		T35	2
read_ops[0x0b]	689	1			T2	4		T10	7		T13	9
read_ops[0x3b]	717	1			T2	7		T10	7		T35	2
read_ops[0x6b]	707	1			T2	4		T4	2		T8	2
read_ops[0xbb]	640	1			T2	5		T10	4		T13	8
read_ops[0xeb]	725	1			T2	4		T10	7		T13	6

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T13	1		T19	1		T176	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T33	2		T176	2		T180	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T19	2		T30	1		T189	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T19	1		T30	2		T59	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	17	1			T32	2		T34	2		T72	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T2	1		T28	1		T30	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T31	1		T32	2		T185	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	11	1			T202	1		T23	2		T43	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	248	1			T10	5		T35	1		T13	6
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	273	1			T2	1		T10	5		T35	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T31	1		T32	1		T176	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	23	1			T2	1		T30	1		T33	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T31	1		T32	1		T59	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T29	1		T31	1		T62	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	37	1			T10	1		T13	1		T30	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T19	2		T32	1		T33	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	11	1			T2	1		T13	1		T191	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T30	1		T202	1		T23	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	257	1			T2	2		T10	5		T13	3
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	240	1			T10	1		T13	4		T39	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T35	1		T39	1		T32	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	42	1			T35	1		T39	1		T28	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T28	1		T19	1		T30	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T2	2		T19	1		T30	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T234	1		T192	1		T177	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T2	1		T10	1		T29	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T30	1		T180	1		T193	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T28	1		T19	1		T193	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	271	1			T2	1		T10	4		T13	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	241	1			T2	3		T10	2		T13	5
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T39	1		T163	1		T30	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T2	1		T13	1		T39	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T2	1		T10	2		T19	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T30	1		T31	1		T240	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T2	1		T19	1		T55	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T10	1		T13	1		T28	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T10	1		T180	1		T189	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T31	1		T62	1		T177	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	248	1			T4	1		T8	1		T10	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	262	1			T2	1		T4	1		T8	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T19	3		T30	1		T33	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T19	1		T33	1		T183	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	16	1			T10	1		T13	1		T55	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T30	1		T183	2		T185	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T19	2		T32	1		T34	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T10	1		T19	1		T55	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T30	1		T180	1		T192	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T2	1		T30	1		T198	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	231	1			T10	1		T13	2		T39	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	242	1			T2	4		T10	1		T13	5
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T19	1		T32	1		T33	4
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T10	1		T19	1		T30	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T32	2		T33	2		T180	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T10	1		T62	1		T185	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T2	1		T55	2		T59	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T28	1		T30	1		T32	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T32	2		T33	1		T170	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T79	1		T47	1		T218	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	252	1			T2	2		T10	4		T13	4
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	272	1			T2	1		T10	1		T13	2