Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2445005	1			T1	1		T2	39106		T3	62
all_pins[1]	2445005	1			T1	1		T2	39106		T3	62
all_pins[2]	2445005	1			T1	1		T2	39106		T3	62
all_pins[3]	2445005	1			T1	1		T2	39106		T3	62
all_pins[4]	2445005	1			T1	1		T2	39106		T3	62
all_pins[5]	2445005	1			T1	1		T2	39106		T3	62
all_pins[6]	2445005	1			T1	1		T2	39106		T3	62
all_pins[7]	2445005	1			T1	1		T2	39106		T3	62

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	19441210	1			T1	8		T2	312848		T3	496
values[0x1]	118830	1			T19	17		T59	4		T61	3362
transitions[0x0=>0x1]	116221	1			T19	16		T59	4		T61	2886
transitions[0x1=>0x0]	116233	1			T19	16		T59	4		T61	2886

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2444737	1			T1	1		T2	39106		T3	62
all_pins[0]	values[0x1]	268	1			T19	6		T60	2		T62	3
all_pins[0]	transitions[0x0=>0x1]	228	1			T19	6		T60	2		T62	3
all_pins[0]	transitions[0x1=>0x0]	474	1			T19	1		T61	1		T60	5
all_pins[1]	values[0x0]	2444491	1			T1	1		T2	39106		T3	62
all_pins[1]	values[0x1]	514	1			T19	1		T61	1		T60	5
all_pins[1]	transitions[0x0=>0x1]	380	1			T19	1		T60	5		T62	66
all_pins[1]	transitions[0x1=>0x0]	163	1			T19	2		T59	1		T61	38
all_pins[2]	values[0x0]	2444708	1			T1	1		T2	39106		T3	62
all_pins[2]	values[0x1]	297	1			T19	2		T59	1		T61	39
all_pins[2]	transitions[0x0=>0x1]	254	1			T19	2		T59	1		T61	38
all_pins[2]	transitions[0x1=>0x0]	131	1			T60	3		T62	5		T166	2
all_pins[3]	values[0x0]	2444831	1			T1	1		T2	39106		T3	62
all_pins[3]	values[0x1]	174	1			T61	1		T60	3		T62	6
all_pins[3]	transitions[0x0=>0x1]	124	1			T61	1		T60	3		T62	4
all_pins[3]	transitions[0x1=>0x0]	136	1			T19	2		T61	2		T62	1
all_pins[4]	values[0x0]	2444819	1			T1	1		T2	39106		T3	62
all_pins[4]	values[0x1]	186	1			T19	2		T61	2		T62	3
all_pins[4]	transitions[0x0=>0x1]	151	1			T19	2		T61	2		T62	3
all_pins[4]	transitions[0x1=>0x0]	2758	1			T19	2		T59	1		T61	479
all_pins[5]	values[0x0]	2442212	1			T1	1		T2	39106		T3	62
all_pins[5]	values[0x1]	2793	1			T19	2		T59	1		T61	479
all_pins[5]	transitions[0x0=>0x1]	577	1			T19	1		T59	1		T61	6
all_pins[5]	transitions[0x1=>0x0]	112204	1			T19	2		T61	2364		T62	12029
all_pins[6]	values[0x0]	2330585	1			T1	1		T2	39106		T3	62
all_pins[6]	values[0x1]	114420	1			T19	3		T61	2837		T60	1
all_pins[6]	transitions[0x0=>0x1]	114375	1			T19	3		T61	2836		T60	1
all_pins[6]	transitions[0x1=>0x0]	133	1			T19	1		T59	2		T61	2
all_pins[7]	values[0x0]	2444827	1			T1	1		T2	39106		T3	62
all_pins[7]	values[0x1]	178	1			T19	1		T59	2		T61	3
all_pins[7]	transitions[0x0=>0x1]	132	1			T19	1		T59	2		T61	3
all_pins[7]	transitions[0x1=>0x0]	234	1			T19	6		T60	2		T62	2