Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.63	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	2	126	98.44

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	2	126	98.44	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3151	1			T2	20		T10	104		T13	51
values[1]	3354	1			T2	20		T10	20		T29	35
values[2]	3025	1			T2	28		T10	20		T13	40
values[3]	2756	1			T2	22		T6	18		T35	8
values[4]	3670	1			T4	14		T8	20		T10	180
values[5]	3067	1			T10	40		T13	51		T28	111
values[6]	3255	1			T2	20		T10	20		T13	230
values[7]	3934	1			T10	110		T13	20		T28	216

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3781	1			T6	18		T13	115		T28	53
values[1]	2947	1			T4	14		T10	150		T115	24
values[2]	3390	1			T2	20		T10	20		T13	117
values[3]	3092	1			T2	48		T10	20		T35	8
values[4]	3429	1			T2	22		T10	113		T13	218
values[5]	3434	1			T8	20		T10	20		T92	12
values[6]	3102	1			T2	20		T10	41		T13	20
values[7]	3037	1			T10	130		T13	40		T30	74

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25757

1

T2

110

T4

14

T6

18

auto[1]

455

1

T10

8

T13

7

T28

4

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	2	126	98.44	2

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	[values[4]]	0	1	1
[auto[1]]	[values[6]]	[values[2]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	594	1			T28	20		T174	14		T62	49
auto[0]	values[0]	values[1]	550	1			T10	104		T30	25		T175	48
auto[0]	values[0]	values[2]	287	1			T176	10		T62	20		T177	19
auto[0]	values[0]	values[3]	322	1			T28	20		T59	27		T77	18
auto[0]	values[0]	values[4]	364	1			T13	31		T178	2		T179	22
auto[0]	values[0]	values[5]	491	1			T31	20		T180	20		T181	95
auto[0]	values[0]	values[6]	201	1			T2	20		T13	20		T182	6
auto[0]	values[0]	values[7]	296	1			T183	20		T184	20		T185	55
auto[0]	values[1]	values[0]	347	1			T186	14		T187	14		T188	23
auto[0]	values[1]	values[1]	486	1			T31	86		T183	108		T185	24
auto[0]	values[1]	values[2]	324	1			T2	20		T189	20		T185	20
auto[0]	values[1]	values[3]	267	1			T29	34		T185	33		T188	59
auto[0]	values[1]	values[4]	503	1			T62	52		T190	12		T191	20
auto[0]	values[1]	values[5]	237	1			T32	44		T192	26		T23	20
auto[0]	values[1]	values[6]	440	1			T193	16		T189	19		T185	20
auto[0]	values[1]	values[7]	685	1			T10	20		T62	20		T189	38
auto[0]	values[2]	values[0]	605	1			T13	20		T19	41		T62	20
auto[0]	values[2]	values[1]	379	1			T10	20		T19	20		T32	25
auto[0]	values[2]	values[2]	280	1			T13	20		T28	20		T59	20
auto[0]	values[2]	values[3]	305	1			T2	28		T62	30		T183	37
auto[0]	values[2]	values[4]	297	1			T39	12		T29	20		T30	20
auto[0]	values[2]	values[5]	582	1			T19	20		T192	21		T170	53
auto[0]	values[2]	values[6]	375	1			T29	33		T30	50		T194	10
auto[0]	values[2]	values[7]	150	1			T32	22		T59	22		T195	20
auto[0]	values[3]	values[0]	554	1			T6	18		T13	71		T32	27
auto[0]	values[3]	values[1]	246	1			T69	18		T196	34		T89	12
auto[0]	values[3]	values[2]	398	1			T169	4		T30	46		T34	23
auto[0]	values[3]	values[3]	304	1			T35	8		T197	14		T198	19
auto[0]	values[3]	values[4]	207	1			T2	22		T162	2		T199	12
auto[0]	values[3]	values[5]	399	1			T92	12		T200	14		T185	31
auto[0]	values[3]	values[6]	354	1			T201	6		T185	20		T177	20
auto[0]	values[3]	values[7]	242	1			T13	20		T34	24		T185	20
auto[0]	values[4]	values[0]	267	1			T202	28		T203	28		T23	20
auto[0]	values[4]	values[1]	321	1			T4	14		T10	26		T115	24
auto[0]	values[4]	values[2]	605	1			T13	22		T31	106		T32	19
auto[0]	values[4]	values[3]	582	1			T86	10		T31	46		T32	20
auto[0]	values[4]	values[4]	363	1			T10	111		T93	10		T28	23
auto[0]	values[4]	values[5]	565	1			T8	20		T55	110		T59	20
auto[0]	values[4]	values[6]	455	1			T10	39		T19	137		T204	26
auto[0]	values[4]	values[7]	438	1			T30	18		T31	20		T62	29
auto[0]	values[5]	values[0]	710	1			T28	33		T30	62		T31	28
auto[0]	values[5]	values[1]	210	1			T59	20		T205	4		T62	20
auto[0]	values[5]	values[2]	468	1			T10	20		T13	29		T32	20
auto[0]	values[5]	values[3]	326	1			T28	78		T163	16		T33	24
auto[0]	values[5]	values[4]	282	1			T32	20		T180	19		T23	21
auto[0]	values[5]	values[5]	330	1			T206	18		T62	27		T183	20
auto[0]	values[5]	values[6]	412	1			T207	10		T189	20		T177	45
auto[0]	values[5]	values[7]	287	1			T10	20		T13	20		T30	20
auto[0]	values[6]	values[0]	281	1			T33	25		T192	26		T208	2
auto[0]	values[6]	values[1]	255	1			T180	44		T175	22		T209	2
auto[0]	values[6]	values[2]	241	1			T13	43		T28	34		T175	20
auto[0]	values[6]	values[3]	378	1			T2	20		T19	44		T185	48
auto[0]	values[6]	values[4]	936	1			T13	187		T28	74		T31	20
auto[0]	values[6]	values[5]	370	1			T10	16		T28	27		T19	20
auto[0]	values[6]	values[6]	381	1			T87	6		T210	24		T211	2
auto[0]	values[6]	values[7]	360	1			T30	34		T212	2		T213	21
auto[0]	values[7]	values[0]	342	1			T13	20		T32	19		T33	48
auto[0]	values[7]	values[1]	442	1			T28	20		T30	23		T214	10
auto[0]	values[7]	values[2]	736	1			T28	117		T19	21		T33	54
auto[0]	values[7]	values[3]	557	1			T10	20		T28	77		T30	54
auto[0]	values[7]	values[4]	432	1			T55	19		T31	49		T189	20
auto[0]	values[7]	values[5]	407	1			T59	20		T33	20		T215	6
auto[0]	values[7]	values[6]	419	1			T30	41		T216	6		T180	20
auto[0]	values[7]	values[7]	528	1			T10	90		T31	51		T217	20
auto[1]	values[0]	values[0]	18	1			T183	7		T198	2		T185	1
auto[1]	values[0]	values[1]	15	1			T30	2		T175	2		T218	4
auto[1]	values[0]	values[2]	2	1			T177	1		T219	1		-	-
auto[1]	values[0]	values[3]	2	1			T79	1		T220	1		-	-
auto[1]	values[0]	values[5]	3	1			T23	2		T221	1		-	-
auto[1]	values[0]	values[6]	1	1			T192	1		-	-		-	-
auto[1]	values[0]	values[7]	5	1			T219	5		-	-		-	-
auto[1]	values[1]	values[0]	9	1			T188	2		T43	1		T222	3
auto[1]	values[1]	values[1]	8	1			T183	2		T175	3		T223	3
auto[1]	values[1]	values[2]	5	1			T185	1		T224	1		T225	2
auto[1]	values[1]	values[3]	8	1			T29	1		T226	6		T223	1
auto[1]	values[1]	values[4]	7	1			T62	1		T170	2		T160	2
auto[1]	values[1]	values[5]	6	1			T32	2		T192	2		T227	1
auto[1]	values[1]	values[6]	4	1			T189	1		T185	1		T228	2
auto[1]	values[1]	values[7]	18	1			T189	2		T140	2		T229	2
auto[1]	values[2]	values[0]	9	1			T19	1		T230	4		T219	2
auto[1]	values[2]	values[1]	5	1			T32	1		T231	4		-	-
auto[1]	values[2]	values[2]	4	1			T231	1		T232	1		T45	2
auto[1]	values[2]	values[3]	9	1			T62	2		T233	4		T131	2
auto[1]	values[2]	values[4]	2	1			T234	1		T175	1		-	-
auto[1]	values[2]	values[5]	6	1			T170	1		T23	1		T235	2
auto[1]	values[2]	values[6]	13	1			T29	3		T177	5		T44	1
auto[1]	values[2]	values[7]	4	1			T59	2		T236	2		-	-
auto[1]	values[3]	values[0]	16	1			T13	4		T183	2		T203	1
auto[1]	values[3]	values[1]	2	1			T130	1		T237	1		-	-
auto[1]	values[3]	values[2]	6	1			T34	2		T238	1		T239	3
auto[1]	values[3]	values[3]	6	1			T198	1		T192	1		T23	1
auto[1]	values[3]	values[4]	2	1			T202	2		-	-		-	-
auto[1]	values[3]	values[5]	10	1			T185	1		T177	1		T23	5
auto[1]	values[3]	values[6]	6	1			T240	1		T224	2		T231	2
auto[1]	values[3]	values[7]	4	1			T241	1		T44	1		T231	1
auto[1]	values[4]	values[0]	5	1			T202	2		T43	1		T242	1
auto[1]	values[4]	values[1]	6	1			T130	2		T243	3		T244	1
auto[1]	values[4]	values[2]	12	1			T13	1		T32	2		T202	2
auto[1]	values[4]	values[3]	12	1			T245	2		T246	2		T23	2
auto[1]	values[4]	values[4]	5	1			T10	2		T247	1		T238	2
auto[1]	values[4]	values[5]	10	1			T248	2		T233	4		T249	1
auto[1]	values[4]	values[6]	18	1			T10	2		T19	3		T250	6
auto[1]	values[4]	values[7]	6	1			T30	2		T79	2		T238	1
auto[1]	values[5]	values[0]	14	1			T31	1		T170	1		T79	3
auto[1]	values[5]	values[1]	7	1			T43	3		T233	2		T251	2
auto[1]	values[5]	values[2]	10	1			T13	2		T23	2		T47	2
auto[1]	values[5]	values[3]	2	1			T235	2		-	-		-	-
auto[1]	values[5]	values[4]	2	1			T180	1		T220	1		-	-
auto[1]	values[5]	values[5]	1	1			T161	1		-	-		-	-
auto[1]	values[5]	values[6]	4	1			T177	1		T240	1		T252	2
auto[1]	values[5]	values[7]	2	1			T23	1		T131	1		-	-
auto[1]	values[6]	values[0]	1	1			T23	1		-	-		-	-
auto[1]	values[6]	values[1]	3	1			T180	1		T253	1		T254	1
auto[1]	values[6]	values[3]	10	1			T19	1		T185	3		T23	1
auto[1]	values[6]	values[4]	16	1			T23	5		T255	4		T45	1
auto[1]	values[6]	values[5]	8	1			T10	4		T28	2		T256	2
auto[1]	values[6]	values[6]	9	1			T192	1		T140	1		T256	4
auto[1]	values[6]	values[7]	6	1			T213	1		T240	2		T161	3
auto[1]	values[7]	values[0]	9	1			T32	1		T33	3		T44	1
auto[1]	values[7]	values[1]	12	1			T204	1		T43	1		T47	1
auto[1]	values[7]	values[2]	12	1			T28	1		T33	1		T234	4
auto[1]	values[7]	values[3]	2	1			T28	1		T30	1		-	-
auto[1]	values[7]	values[4]	11	1			T55	1		T31	2		T257	4
auto[1]	values[7]	values[5]	9	1			T188	3		T79	3		T131	1
auto[1]	values[7]	values[6]	10	1			T23	4		T258	1		T238	4
auto[1]	values[7]	values[7]	6	1			T191	2		T23	3		T239	1