Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1605

1

T2

6

T3

2

T13

1

auto[1]

1771

1

T2

6

T13

2

T15

8

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1763

1

T2

10

T3

2

T13

3

auto[1]

1613

1

T2

2

T15

3

T17

41

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2670

1

T2

8

T3

1

T13

3

auto[1]

706

1

T2

4

T3

1

T15

3

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	642	1			T2	2		T15	3		T17	7
valid[1]	685	1			T2	3		T3	1		T13	2
valid[2]	714	1			T2	2		T15	4		T17	8
valid[3]	653	1			T2	1		T15	3		T17	9
valid[4]	682	1			T2	4		T3	1		T13	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	108	1			T15	1		T41	1		T32	1
auto[0]	auto[0]	valid[0]	auto[1]	129	1			T2	1		T17	4		T19	1
auto[0]	auto[0]	valid[1]	auto[0]	97	1			T13	1		T327	1		T312	2
auto[0]	auto[0]	valid[1]	auto[1]	165	1			T2	1		T17	5		T59	1
auto[0]	auto[0]	valid[2]	auto[0]	103	1			T15	1		T32	1		T59	2
auto[0]	auto[0]	valid[2]	auto[1]	166	1			T15	1		T17	7		T59	1
auto[0]	auto[0]	valid[3]	auto[0]	91	1			T32	1		T61	1		T312	1
auto[0]	auto[0]	valid[3]	auto[1]	133	1			T17	2		T59	1		T33	2
auto[0]	auto[0]	valid[4]	auto[0]	117	1			T2	2		T3	1		T15	1
auto[0]	auto[0]	valid[4]	auto[1]	151	1			T17	2		T329	2		T330	1
auto[0]	auto[1]	valid[0]	auto[0]	106	1			T2	1		T15	1		T20	1
auto[0]	auto[1]	valid[0]	auto[1]	153	1			T17	3		T32	1		T61	1
auto[0]	auto[1]	valid[1]	auto[0]	113	1			T2	1		T13	1		T20	1
auto[0]	auto[1]	valid[1]	auto[1]	174	1			T17	4		T33	1		T61	1
auto[0]	auto[1]	valid[2]	auto[0]	124	1			T15	1		T20	1		T41	1
auto[0]	auto[1]	valid[2]	auto[1]	191	1			T17	1		T59	1		T331	1
auto[0]	auto[1]	valid[3]	auto[0]	99	1			T15	1		T31	1		T42	1
auto[0]	auto[1]	valid[3]	auto[1]	190	1			T15	1		T17	7		T19	1
auto[0]	auto[1]	valid[4]	auto[0]	99	1			T2	2		T13	1		T15	1
auto[0]	auto[1]	valid[4]	auto[1]	161	1			T15	1		T17	6		T59	2
auto[1]	auto[0]	valid[0]	auto[0]	61	1			T15	1		T32	3		T33	1
auto[1]	auto[0]	valid[1]	auto[0]	61	1			T3	1		T19	1		T59	1
auto[1]	auto[0]	valid[2]	auto[0]	69	1			T2	2		T59	1		T33	1
auto[1]	auto[0]	valid[3]	auto[0]	73	1			T32	1		T59	2		T62	1
auto[1]	auto[0]	valid[4]	auto[0]	81	1			T41	1		T42	2		T59	1
auto[1]	auto[1]	valid[0]	auto[0]	85	1			T59	1		T33	2		T61	4
auto[1]	auto[1]	valid[1]	auto[0]	75	1			T2	1		T42	1		T59	1
auto[1]	auto[1]	valid[2]	auto[0]	61	1			T15	1		T20	2		T21	2
auto[1]	auto[1]	valid[3]	auto[0]	67	1			T2	1		T15	1		T41	1
auto[1]	auto[1]	valid[4]	auto[0]	73	1			T59	1		T33	1		T313	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal