Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45206

1

T2

300

T3

12

T13

114

auto[1]

15367

1

T2

61

T15

30

T17

395

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44174

1

T2

251

T3

8

T13

88

auto[1]

16399

1

T2

110

T3

4

T13

26

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	31304	1			T2	180		T3	5		T13	63
others[1]	5104	1			T2	35		T13	8		T15	23
others[2]	5086	1			T2	34		T3	1		T13	5
others[3]	5719	1			T2	40		T3	2		T13	15
interest[1]	3330	1			T2	15		T13	4		T15	16
interest[4]	20450	1			T2	118		T3	2		T13	47
interest[64]	10030	1			T2	57		T3	4		T13	19

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	14715	1			T2	103		T3	4		T13	53
auto[0]	auto[0]	others[1]	2454	1			T2	11		T13	6		T15	15
auto[0]	auto[0]	others[2]	2477	1			T2	17		T3	1		T13	4
auto[0]	auto[0]	others[3]	2712	1			T2	23		T3	1		T13	8
auto[0]	auto[0]	interest[1]	1632	1			T2	9		T13	4		T15	8
auto[0]	auto[0]	interest[4]	9551	1			T2	65		T3	2		T13	38
auto[0]	auto[0]	interest[64]	4817	1			T2	27		T3	2		T13	13
auto[0]	auto[1]	others[0]	8108	1			T2	24		T15	13		T17	203
auto[0]	auto[1]	others[1]	1284	1			T2	7		T15	3		T17	32
auto[0]	auto[1]	others[2]	1253	1			T2	10		T15	5		T17	32
auto[0]	auto[1]	others[3]	1420	1			T2	9		T15	3		T17	38
auto[0]	auto[1]	interest[1]	829	1			T2	2		T17	25		T41	3
auto[0]	auto[1]	interest[4]	5379	1			T2	18		T15	5		T17	129
auto[0]	auto[1]	interest[64]	2473	1			T2	9		T15	6		T17	65
auto[1]	auto[0]	others[0]	8481	1			T2	53		T3	1		T13	10
auto[1]	auto[0]	others[1]	1366	1			T2	17		T13	2		T15	5
auto[1]	auto[0]	others[2]	1356	1			T2	7		T13	1		T15	9
auto[1]	auto[0]	others[3]	1587	1			T2	8		T3	1		T13	7
auto[1]	auto[0]	interest[1]	869	1			T2	4		T15	8		T19	2
auto[1]	auto[0]	interest[4]	5520	1			T2	35		T13	9		T15	35
auto[1]	auto[0]	interest[64]	2740	1			T2	21		T3	2		T13	6

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal