Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	751	1			T19	7		T59	4		T61	7
all_values[1]	751	1			T19	7		T59	4		T61	7
all_values[2]	751	1			T19	7		T59	4		T61	7
all_values[3]	751	1			T19	7		T59	4		T61	7
all_values[4]	751	1			T19	7		T59	4		T61	7
all_values[5]	751	1			T19	7		T59	4		T61	7
all_values[6]	751	1			T19	7		T59	4		T61	7
all_values[7]	751	1			T19	7		T59	4		T61	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3123

1

T19

28

T59

14

T61

32

auto[1]

2885

1

T19

28

T59

18

T61

24

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2457

1

T19

21

T59

14

T61

19

auto[1]

3551

1

T19

35

T59

18

T61

37

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3485

1

T19

34

T59

19

T61

29

auto[1]

2523

1

T19

22

T59

13

T61

27

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	160	1			T19	1		T59	1		T61	2
all_values[0]	auto[0]	auto[0]	auto[1]	65	1			T59	1		T61	2		T60	1
all_values[0]	auto[0]	auto[1]	auto[0]	142	1			T60	1		T62	1		T166	4
all_values[0]	auto[0]	auto[1]	auto[1]	75	1			T19	3		T60	1		T62	1
all_values[0]	auto[1]	auto[0]	auto[1]	152	1			T59	1		T61	3		T60	1
all_values[0]	auto[1]	auto[1]	auto[1]	157	1			T19	3		T59	1		T60	1
all_values[1]	auto[0]	auto[0]	auto[0]	143	1			T62	7		T166	4		T167	3
all_values[1]	auto[0]	auto[0]	auto[1]	80	1			T19	2		T61	3		T62	1
all_values[1]	auto[0]	auto[1]	auto[0]	138	1			T19	2		T59	3		T61	1
all_values[1]	auto[0]	auto[1]	auto[1]	82	1			T60	3		T62	1		T166	2
all_values[1]	auto[1]	auto[0]	auto[1]	165	1			T19	2		T61	2		T60	1
all_values[1]	auto[1]	auto[1]	auto[1]	143	1			T19	1		T59	1		T61	1
all_values[2]	auto[0]	auto[0]	auto[0]	150	1			T19	1		T59	1		T60	4
all_values[2]	auto[0]	auto[0]	auto[1]	97	1			T19	1		T59	1		T61	2
all_values[2]	auto[0]	auto[1]	auto[0]	123	1			T19	1		T61	1		T60	2
all_values[2]	auto[0]	auto[1]	auto[1]	72	1			T61	1		T167	1		T168	1
all_values[2]	auto[1]	auto[0]	auto[1]	174	1			T19	1		T61	2		T60	1
all_values[2]	auto[1]	auto[1]	auto[1]	135	1			T19	3		T59	2		T61	1
all_values[3]	auto[0]	auto[0]	auto[0]	148	1			T19	3		T61	1		T60	1
all_values[3]	auto[0]	auto[0]	auto[1]	59	1			T19	1		T59	1		T62	2
all_values[3]	auto[0]	auto[1]	auto[0]	137	1			T19	2		T59	2		T61	3
all_values[3]	auto[0]	auto[1]	auto[1]	71	1			T60	1		T62	2		T166	1
all_values[3]	auto[1]	auto[0]	auto[1]	191	1			T19	1		T59	1		T61	3
all_values[3]	auto[1]	auto[1]	auto[1]	145	1			T60	2		T62	4		T166	1
all_values[4]	auto[0]	auto[0]	auto[0]	164	1			T19	1		T59	1		T61	4
all_values[4]	auto[0]	auto[0]	auto[1]	75	1			T19	1		T62	4		T166	2
all_values[4]	auto[0]	auto[1]	auto[0]	126	1			T19	1		T59	2		T166	2
all_values[4]	auto[0]	auto[1]	auto[1]	76	1			T19	2		T62	1		T166	4
all_values[4]	auto[1]	auto[0]	auto[1]	163	1			T19	2		T59	1		T61	1
all_values[4]	auto[1]	auto[1]	auto[1]	147	1			T61	2		T62	4		T166	2
all_values[5]	auto[0]	auto[0]	auto[0]	207	1			T19	3		T59	1		T61	1
all_values[5]	auto[0]	auto[1]	auto[0]	232	1			T19	1		T59	1		T61	2
all_values[5]	auto[1]	auto[0]	auto[1]	157	1			T59	1		T61	3		T60	2
all_values[5]	auto[1]	auto[1]	auto[1]	155	1			T19	3		T59	1		T61	1
all_values[6]	auto[0]	auto[0]	auto[0]	154	1			T19	1		T61	1		T62	5
all_values[6]	auto[0]	auto[0]	auto[1]	71	1			T59	1		T60	2		T62	2
all_values[6]	auto[0]	auto[1]	auto[0]	141	1			T19	1		T59	1		T61	1
all_values[6]	auto[0]	auto[1]	auto[1]	69	1			T19	1		T62	3		T168	1
all_values[6]	auto[1]	auto[0]	auto[1]	155	1			T19	2		T59	1		T61	1
all_values[6]	auto[1]	auto[1]	auto[1]	161	1			T19	2		T59	1		T61	4
all_values[7]	auto[0]	auto[0]	auto[0]	166	1			T19	2		T60	2		T62	5
all_values[7]	auto[0]	auto[0]	auto[1]	66	1			T19	2		T60	1		T166	1
all_values[7]	auto[0]	auto[1]	auto[0]	126	1			T19	1		T59	1		T61	2
all_values[7]	auto[0]	auto[1]	auto[1]	70	1			T59	1		T61	2		T62	1
all_values[7]	auto[1]	auto[0]	auto[1]	161	1			T19	1		T59	1		T61	1
all_values[7]	auto[1]	auto[1]	auto[1]	162	1			T19	1		T59	1		T61	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal