Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2858161	1			T1	1		T2	1		T3	12685
all_values[1]	2858161	1			T1	1		T2	1		T3	12685
all_values[2]	2858161	1			T1	1		T2	1		T3	12685
all_values[3]	2858161	1			T1	1		T2	1		T3	12685
all_values[4]	2858161	1			T1	1		T2	1		T3	12685
all_values[5]	2858161	1			T1	1		T2	1		T3	12685
all_values[6]	2858161	1			T1	1		T2	1		T3	12685
all_values[7]	2858161	1			T1	1		T2	1		T3	12685

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21470778

1

T1

8

T2

8

T3

101480

auto[1]

1394510

1

T18

49

T77

68

T78

90

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22843235

1

T1

8

T2

8

T3

101257

auto[1]

22053

1

T3

223

T18

31

T31

1

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2573268	1			T1	1		T2	1		T3	12561
all_values[0]	auto[0]	auto[1]	11337	1			T3	124		T18	4		T77	3
all_values[0]	auto[1]	auto[0]	272681	1			T18	6		T77	5		T78	4
all_values[0]	auto[1]	auto[1]	875	1			T77	7		T78	6		T33	1
all_values[1]	auto[0]	auto[0]	2732083	1			T1	1		T2	1		T3	12602
all_values[1]	auto[0]	auto[1]	5165	1			T3	83		T18	1		T77	5
all_values[1]	auto[1]	auto[0]	120518	1			T18	7		T77	5		T78	3
all_values[1]	auto[1]	auto[1]	395	1			T77	2		T78	6		T170	4
all_values[2]	auto[0]	auto[0]	2605000	1			T1	1		T2	1		T3	12669
all_values[2]	auto[0]	auto[1]	1842	1			T3	16		T18	2		T77	7
all_values[2]	auto[1]	auto[0]	251045	1			T18	5		T77	3		T78	12
all_values[2]	auto[1]	auto[1]	274	1			T77	5		T78	2		T33	3
all_values[3]	auto[0]	auto[0]	2696746	1			T1	1		T2	1		T3	12685
all_values[3]	auto[0]	auto[1]	229	1			T18	2		T77	3		T78	3
all_values[3]	auto[1]	auto[0]	160983	1			T18	3		T77	5		T78	9
all_values[3]	auto[1]	auto[1]	203	1			T18	5		T77	2		T78	2
all_values[4]	auto[0]	auto[0]	2655395	1			T1	1		T2	1		T3	12685
all_values[4]	auto[0]	auto[1]	196	1			T18	1		T77	5		T78	4
all_values[4]	auto[1]	auto[0]	202339	1			T18	2		T77	2		T78	7
all_values[4]	auto[1]	auto[1]	231	1			T18	5		T77	4		T78	4
all_values[5]	auto[0]	auto[0]	2800036	1			T1	1		T2	1		T3	12685
all_values[5]	auto[0]	auto[1]	333	1			T18	1		T31	1		T77	4
all_values[5]	auto[1]	auto[0]	57600	1			T18	2		T77	7		T78	5
all_values[5]	auto[1]	auto[1]	192	1			T18	1		T77	2		T78	4
all_values[6]	auto[0]	auto[0]	2632046	1			T1	1		T2	1		T3	12685
all_values[6]	auto[0]	auto[1]	211	1			T18	2		T77	5		T33	1
all_values[6]	auto[1]	auto[0]	225732	1			T18	5		T77	7		T78	9
all_values[6]	auto[1]	auto[1]	172	1			T18	1		T77	1		T78	5
all_values[7]	auto[0]	auto[0]	2756699	1			T1	1		T2	1		T3	12685
all_values[7]	auto[0]	auto[1]	192	1			T18	2		T78	5		T33	2
all_values[7]	auto[1]	auto[0]	101064	1			T18	3		T77	8		T78	11
all_values[7]	auto[1]	auto[1]	206	1			T18	4		T77	3		T78	1