Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	28411	1			T1	4		T3	279		T8	4
auto[SpiFlashAddrCfg]	6027	1			T1	4		T3	33		T13	4
auto[SpiFlashAddr3b]	7438	1			T1	6		T3	37		T6	6
auto[SpiFlashAddr4b]	6328	1			T1	6		T3	25		T8	6

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27541

1

T3

135

T6

6

T8

14

auto[1]

20663

1

T1

20

T3

239

T11

14

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25760

1

T1

12

T3

205

T6

6

auto[1]

22444

1

T1

8

T3

169

T8

10

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	32137	1			T1	4		T3	293		T8	8
values[1]	878	1			T3	7		T47	7		T35	3
values[2]	1264	1			T3	6		T11	2		T24	4
values[3]	1213	1			T1	2		T3	3		T6	4
values[4]	1183	1			T3	11		T16	6		T23	2
values[5]	1171	1			T1	2		T3	1		T11	2
values[6]	1210	1			T1	2		T3	5		T6	2
values[7]	1235	1			T1	2		T3	10		T47	8
values[8]	7913	1			T1	8		T3	38		T8	6

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24539

1

T1

20

T6

6

T8

14

auto[1]

23665

1

T3

374

T47

295

T59

125

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

46410

1

T1

20

T3

355

T6

6

write

1794

1

T3

19

T15

2

T24

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

16380

1

T1

12

T3

74

T6

2

valids[0x1]

31824

1

T1

8

T3

300

T6

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1348	1			T3	11		T23	2		T39	2
internal_process_ops[0x5a]	1289	1			T3	4		T8	4		T39	2
internal_process_ops[0x05]	16671	1			T3	190		T8	2		T12	4
internal_process_ops[0x35]	1326	1			T1	2		T3	10		T47	5
internal_process_ops[0x15]	1261	1			T1	2		T3	8		T8	4
internal_process_ops[0x03]	926	1			T3	3		T23	4		T38	6
internal_process_ops[0x0b]	851	1			T3	4		T11	2		T12	2
internal_process_ops[0x3b]	879	1			T1	2		T6	2		T13	2
internal_process_ops[0x6b]	897	1			T3	4		T12	2		T23	2
internal_process_ops[0xbb]	839	1			T1	4		T24	2		T38	8
internal_process_ops[0xeb]	855	1			T1	2		T3	3		T39	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47356

1

T1

20

T3

366

T6

6

auto[1]

848

1

T3

8

T32

1

T47

6

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46467

1

T1

20

T3

354

T6

6

auto[1]

1737

1

T3

20

T24

2

T32

2

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8231

1

T8

4

T13

2

T14

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

4976

1

T1

4

T11

4

T32

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1701

1

T13

4

T12

2

T23

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1534

1

T1

4

T32

11

T35

33

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2139

1

T6

6

T8

4

T16

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1735

1

T1

6

T11

2

T32

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1733

1

T8

6

T15

2

T23

12

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1612

1

T1

6

T11

8

T32

7

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

69

1

T24

2

T170

2

T171

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

55

1

T170

1

T44

3

T45

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

57

1

T35

3

T73

1

T33

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

43

1

T41

1

T170

3

T44

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

80

1

T32

2

T35

1

T50

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

39

1

T35

1

T34

1

T41

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

28

1

T33

2

T34

2

T170

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

50

1

T32

1

T34

3

T40

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

52

1

T35

1

T172

2

T44

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

46

1

T35

3

T41

1

T45

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

66

1

T35

5

T37

1

T73

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

67

1

T35

2

T33

3

T40

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

55

1

T15

2

T50

2

T34

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

49

1

T35

2

T73

1

T33

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

64

1

T35

3

T41

2

T44

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

58

1

T37

3

T33

1

T41

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8695

1

T3

74

T47

139

T59

97

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6029

1

T3

195

T47

30

T59

4

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1244

1

T3

18

T47

18

T59

3

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1151

1

T3

9

T47

16

T59

1

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1641

1

T3

20

T47

29

T59

3

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1477

1

T3

14

T47

18

T59

5

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1245

1

T3

15

T47

16

T59

4

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1267

1

T3

10

T47

18

T59

5

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

64

1

T3

5

T60

4

T92

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

64

1

T173

1

T92

2

T70

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

69

1

T3

1

T90

2

T92

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

59

1

T3

4

T47

1

T90

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

59

1

T47

4

T60

1

T87

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

50

1

T3

1

T47

3

T59

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

50

1

T3

3

T174

2

T175

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

41

1

T3

2

T90

1

T70

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

52

1

T3

2

T47

1

T90

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

62

1

T87

2

T90

2

T92

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

57

1

T59

1

T60

3

T87

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

44

1

T3

1

T60

1

T173

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

62

1

T55

1

T174

1

T175

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

54

1

T60

1

T92

3

T55

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

62

1

T87

1

T174

2

T176

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

67

1

T47

2

T92

2

T55

3

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3463	1			T8	4		T13	2		T14	2
auto[0]	values[0]	valids[0x1]	11962	1			T1	4		T8	4		T11	2
auto[0]	values[1]	valids[0x1]	438	1			T35	3		T37	1		T36	2
auto[0]	values[2]	valids[0x0]	476	1			T11	2		T39	4		T32	3
auto[0]	values[2]	valids[0x1]	203	1			T24	4		T39	2		T35	4
auto[0]	values[3]	valids[0x0]	446	1			T1	2		T15	2		T35	4
auto[0]	values[3]	valids[0x1]	280	1			T6	4		T32	2		T35	5
auto[0]	values[4]	valids[0x0]	439	1			T23	2		T39	4		T32	2
auto[0]	values[4]	valids[0x1]	264	1			T16	6		T35	6		T34	4
auto[0]	values[5]	valids[0x0]	454	1			T1	2		T11	2		T12	2
auto[0]	values[5]	valids[0x1]	225	1			T24	2		T33	4		T34	1
auto[0]	values[6]	valids[0x0]	452	1			T1	2		T6	2		T35	7
auto[0]	values[6]	valids[0x1]	231	1			T35	1		T33	4		T34	1
auto[0]	values[7]	valids[0x0]	411	1			T35	4		T52	2		T73	2
auto[0]	values[7]	valids[0x1]	272	1			T1	2		T35	4		T73	2
auto[0]	values[8]	valids[0x0]	2864	1			T1	6		T13	2		T11	4
auto[0]	values[8]	valids[0x1]	1659	1			T1	2		T8	6		T13	2
auto[1]	values[0]	valids[0x0]	3525	1			T3	40		T47	53		T59	6
auto[1]	values[0]	valids[0x1]	13187	1			T3	253		T47	157		T59	104
auto[1]	values[1]	valids[0x1]	440	1			T3	7		T47	7		T59	1
auto[1]	values[2]	valids[0x0]	360	1			T3	4		T47	2		T60	6
auto[1]	values[2]	valids[0x1]	225	1			T3	2		T59	1		T60	1
auto[1]	values[3]	valids[0x0]	286	1			T3	3		T47	2		T87	4
auto[1]	values[3]	valids[0x1]	201	1			T60	3		T34	2		T90	1
auto[1]	values[4]	valids[0x0]	272	1			T3	7		T47	5		T57	3
auto[1]	values[4]	valids[0x1]	208	1			T3	4		T47	3		T57	2
auto[1]	values[5]	valids[0x0]	293	1			T3	1		T47	4		T59	1
auto[1]	values[5]	valids[0x1]	199	1			T47	1		T34	2		T90	7
auto[1]	values[6]	valids[0x0]	314	1			T3	2		T47	2		T87	4
auto[1]	values[6]	valids[0x1]	213	1			T3	3		T47	7		T59	1
auto[1]	values[7]	valids[0x0]	339	1			T3	4		T47	7		T60	4
auto[1]	values[7]	valids[0x1]	213	1			T3	6		T47	1		T60	3
auto[1]	values[8]	valids[0x0]	1986	1			T3	13		T47	31		T59	3
auto[1]	values[8]	valids[0x1]	1404	1			T3	25		T47	13		T59	8